Hey *,

how would you solve this problem.

i like to 16bit-INC/DEC a value stored under address ptr1 (zp).



While INC looks kind of ok (but still I'm sure there would a better way) I have so my doubts about the DEC routine I wrote:



Any suggestions to realize this more effectively?

grtx and thx,
\twh

Off the top of my head, this is what I could come up with.



If there is any way you can cache values you use frequently in direct-page, though, do so. There's a huge performance improvement if you do.

All you're really doing is a hard coded 16 bit addition
or subtraction of 1



You don't explicitly set y to begin, but presumably y is 0
so you can iny instead of ldy #1 and save a byte

If you start with 1 in the accumulator, the only way to end up
with 0 in the accumulator after an adc is to add FF and that will
also result in the carry being set, so the sec is redundant.

Your code becomes:



personally, I'd code it like this:



Just because it's a little easier (for me, any way)
to see what's going on.

Dec can be roughly the same.
0 is the only thing you can start with in the accumulator
and subtract 1 from and end up with a barrow, ie
with the carry clear, and that will leave FF in the
accumulator. Adding FF to something is the same
as subtracting 1 (as far as the resulting byte and
ignoring flags)



The last three instructions are the same so they
can probably be shared if that seems desriable,
but I'll leave that as an 'exercise for the reader'

twh1st, your increment needs an LDY #0 near the beginning. Then your LDY #1 can be shortened to INY (which requires re-adjusting your branch distance-- a good reason to use labels). Otherwise it looks ok.

Then you can modify the increment routine to make the decrement routine this way:

kc5tja's TAX INX/DEX TXA is necessary if you're using the old NMOS 6502. If you're not using a Commodore 64 or something where you're stuck with NMOS, I always recommend using the CMOS 6502 instead, partly for the added instructions.

If you're on a 65816 and have both the accumulator and index registers in 16-bit mode, I think you can do:

although I have been away from this stuff for awhile and might need some refresher time.

Edit: I see bogax posted while I was writing. Good post.

Your INC 0,X isn't going to work, because PTR1 points to the variable to be in/decremented. You have to use (dp),Y for this, unless INC/DEC take (0,X) as an addressing mode (I can't recall off-hand if it does).

If using the 65816 in 16-bit mode, though, I'd use this:

Ah yes, just take the # out of the LDX #. Now you'll get the final address in X, having loaded it from the pointer variable. So if PTR1 at address 0061-0062 for example contained 3FE6, now you'll increment the 16-bit number contained at 3FE6-3FE7.

excellent!!! thank you guys!

btw, I forgot to copy'n'paste the "ldy #0" .. it was not meant to be set implicitly.

grtx,
\twh

I'm coding with an Atari 8bit. I never heard of different 6502 implementations like CMOS or NMOS. So I guess I have a NMOS 6502 because I never saw opcodes like "DEA" or "INA".

thanks anyway!!

grtx,
\twh

Hi twh,

the Atari 8bit has a NMOS CPU, you might have a CMOS Type in your floppy when you have a Speed Enhancement in there (The Compyshop Speedy is using a 65C02). Unfortunately, in the Atari XL/XE line, there is now easy way to replace the NMOS 6502 for a CMOS one, because the Atari 6502 has this special "halt" signal for sharing the bus with Antic. I've read that it is possible to exchange the CPU in old Atari 800 machines, as they use a stock 6502 NMOS (and not the special Atari one).

Carsten

Shouldn't /RDY be a replacement to halt? You can pause the CPU as long as you need with /RDY if I recall correctly.

RDY is active-high -- no overbar for the signal name. So, if RDY goes low it will halt the processor. However, it will not release the bus. For this, a separate signal (BE for the 65816 at least; not sure if BE also exists on 65C02 as well) is used. If BE doesn't exist on the 65C02, external, three-statable bus buffering is required.

And I take it the 65c02 or 65cs02 do not have buffers on the processor side to protect from another device trying to drive the same address bus? (not necessarily tri-state)

Like if the processor is halted via /RDY and the address bus has a random (but static while paused) value asserted by the CPU - you could have a logic device that would sort of invert the state of the address lines for another device to drive the address bus. Lines that are driven high by the original processor could be pulled to low and vice versa when needed by the another processor. I'm not sure if this would damage the original CPU or not.

WDC's 65c02 does have BE (active-high bus enable) on pin 36 of the DIP, 40 of the PLCC, and 34 of the PQFP. (It's the same pin on the PLCC and PQFP, but they're numbered differently, the PLCC starting with pin 1 in the middle of the top and the PQFP starting on the corner.) They also have a ML\ (active-low memory lock) output (pin 5 of the DIP) and an VP\ (active-low vector pull) output (pin 1 of the DIP where other manufacturers had ground). Pin 21 of the DIP is still ground. WDC's 65c02 also lets you stop the clock indefinitely in either phase.

In fact, internally to the CPU chip itself, that's all RDY does -- it simply gates the clock in phase-1!!