My original intent was to keep this thread short and concise without becoming a mega-thread like some of my other projects here, but I also must make regular updates or details will get lost.

Today I modified ISE 14.7 to work under Win10x64 like in the topic I linked to above and ISE iMPACT is now working. I had to load an old project file and iMPACT was instantly available. So then I plugged in the board and powered it up and it recognized the 2 FPGA's and the SPI 'PROMs' that were connected to them.

On a side note my main desktop computer motherboard appears to have cashed itself out. I'm not quite sure what to do with that mess right now...

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

Now the bad news is I couldn't program/verify/erase the SPI FLASH's, although I could program the FPGA's directly. Nice to know there is that option... I realized I forgot I was still using the W25Q80EW, the 1.8V devices from the old design. No doubt those won't function properly when fed 3.3V!

The proper Winbond device to use is the W25Q80DV. I've ordered 2 of them with quick shipping. However, even these are abit of a gamble because they have not been tested & verified by Xilinx. The Winbond IC's that are spec'd to work in Xilinx' Introduction to indirect programming with the Spartan 6 are EOL. I'll just have to trust that the new FLASH families from Winbond are backwards compatible. I couldn't find that fact in the datasheet.

BTW, I realized I've neglected to mention the JTAG programming cable I use is from Digilent. I think it was the HS-1 which isn't sold anymore. There's currently the HS-2 and HS-3 available from Digilent. I'm sure there's more options... I'll notate this in the head post.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

ElEctric_EyE:

Many years ago I was able to modify the AMD Flash Programming module used in their monitor to program compatible, non-AMD Flash parts. More recently, I had my team create an SPI Flash programming module that we loaded into the FPGA using JTAG, and which would program non-Xilinx approved SPI Flash parts using the Ethernet connection to the FPGA. After that initial program load and configuration of the boot SPI FLash, all subsequent reprogramming of the SPI Flash was through the Ethernet interface. From that point forward, my team has never been stymied by whether an SPI Flash was supported or not by the Xilinx-supplied JTAG SPI Flash programmer.

Its been my experience that the Xilinx-supplied JTAG SPI Flash programmer is very difficult to use with any parts except those listed in their documentation for each FPGA family that supports booting from SPI Flash. I hate to suggest it, because it entails a bit of work, but the most convenient way to handle this situation, and become independent of the vendor's IP, is to build your own SPI Flash programmer module that uses an interface such as a serial port (RS-232 or Ethernet) to download, program, and verify the external boot SPI Flash devices that you intend on using.

_________________
Michael A.

Michael, thanks for your input! It's highly valued. However, my initial thought before even doing the board layout was that if this doesn't work, I'd go back to using Xilinx PROMs. In my case I'd be using the XCF04S. The 20-pin TSSOP footprint isn't much larger than the SPI FLASH I'm currently using. The 2 drawbacks are cost @ $14.60 vs $.51 and the board layout would have to be redone which means another $150. We shall see. I have high hopes as Arlet has used the older SPI FLASHs with success here in his 6502 Sandbox project. One more option before I totally give up on SPI FLASH is to look at the Digilent website for Spartan 6 boards and check out their schematics. I already did 1 quick check there on one particular board and the SPI FLASH they used was also EOL.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

I got in the Winbond W25Q80DV SPI FLASH's and was able to perform all the functions from iMPACT like erase, program, verify etc. on the first FLASH only. It is not recognizing the 2nd SPI FLASH in the chain. From iMPACT I choose the W25Q80BV legacy device and it does indeed seem the newer DV FLASH's are backwards compatible with the BV FLASH's. Now I have to figure out what gives with the 2nd FLASH.

EDIT: It's not only the 2nd FLASH in the chain, it's the 2nd FPGA as well with an error message 'Done signal was not high'. I consider this actually good news, only because ISE does see both FPGA's and both SPI FLASH's attached to each FPGA. More testing tomorrow...

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

After a couple more unsuccessful experiments, I think it's wise to abandon the daisy chain configuration. I'll redesign the board for 2 JTAG connectors. 1 great thing I took away from this 1st stage is that the Winbond W25Q80DV appears to work with ISE 14.7. I think it's time to stock up on these!

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

I think I realized why my original dual SPI setup wouldn't work. I missed the fact in the UG380, daisy chaining section that DOut of the first FPGA must connect to DIn of the second FPGA. With my setup, using 2 SPI FLASH's 1 per FPGA, each DIn had to go to each FLASH IC... Anyway, it all worked out in the end because I failed to realize 1 small detail. I wanted these boards to be functional with either FPGA present and not necessarily both. Now that idea is going to be fully realized. The V1.6 Boards have been ordered! The focus will again be on JTAG, but after that I think it'll be time for a RAM and videoDAC on the slave/bottom FPGA with the keyboard/PC interface. Hopefully JTAG testing will be quick!

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

Progress update: Got the V1.6 boards in, also the necessary parts to start fresh. 2 more FPGA's, 2 FPGA FLASHs, 2 DS1818s, resistors, voltage regulators and updated JTAG connectors. The only parts I'm salvaging is the main Power In receptacle and FPGA reset buttons. More progress should be made by this weekend at the very latest. I'm starting tonight.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

1st attempt, I screwed up and swiped the FPGA pins while soldering and bent them. 1st board was trashed, there was no saving them and they were new parts. I was so pisst yesterday...

After regathering my mental strength, today I desoldered the FPGA's from the V1.5 board where the daisy chain JTAG wasn't functional. I successfully soldered them to a 2nd V1.6 board along with new VReg's and JTAG related stuff. JTAG does appear to be functional for both FPGA SPI FLASHs (W25Q80DV). I chose the legacy device W25Q80BV in ISE14.7. Whew!!

I plow forward with the videoDAC, SyncRAM, I2C and the Si514 programmable Oscillator next.

Here's a couple pics... I soldered in a couple 0603 4.7K resistors on pads meant for 0402 (on the bottom). I was out of the 0402, so I tried what I had and they actually fit very nicely!

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

You did well to desolder parts with so many pins!

Yes, I used the hot plate for those 2. After about 20 seconds they came off very even and clean. My confidence was high that I could reuse them, since they weren't overtly abused by heat.

Yesterday I soldered in the 48-pin QFP videoDAC and associated passives, 2 SyncRAM's (1 for each S6), the pullup resistors for I2C, the VGA connector and 3 ferrite beads which are used as power supply filters to some IC's. There is 1 ferrite bead used for the videoDAC and 2 for the digital audio transceiver. Then the board got another ultrasonic clean in 91% isopropyl alcohol. Then I packaged it in an anti-static bag.

As I progress, I find myself gravitating towards a different technique. I use liquid flux now, the ChipQuik CQ4LF-1.0 and fluxless .015" silver bearing solder. This is the way to go! No solder bridges. I hate them! I prefer quick, clean and neat. No cleaning up messes...

Anyway, today after work, I unpacked the board hooked up the 5V main and threw the PS switch. Last time I did this I heard a pop and a ferrite bead jumped off the board! I was fully expecting smoke. But none. And ISE 14.7 saw the S6 and SPI PROMs!

This is a milestone. I can now begin to configure the constraints file to assign FPGA pins to the SyncRAMs and videoDAC. I already have a project to do an initial test.

A sidenote: The Si514 has a slightly different pinout than the Si570. The I2C signals are on different pins. Luckily, the pad spacing is the same for the power and Freq out. I may be able to correct this without ordering new boards.

A pic of the top board as it progresses. Nothing much changed on the bottom yet.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

Here's what I'm dealing with regarding my mistake from switching from the Si570 to the Si514. I'm thinking of routing .014" wirewrap underneath the Si514. This board was designed for the Si570, but during the interim Silicon Labs came out with a much more capable IC and I had forgotten to update the land pattern. Pretty much a 2 short right angle wire wrap wires solder to the pads, then the Si514 ontop. Gonna be loads of solder for all the pins to make up for that ~.020 gap...

I'll work on it tomorrow, then fire up the old o'scope.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

I wired in the Si514 I and was expecting 40MHz out of this device as they are pre-programmed before shipping from Silicon Labs. But what I measured with my scope was right on the bottom limit of this oscillator ~@173kHz. It didn't look like a square wave either, more like a saw tooth waveform. I'll have to look into this...

The 3.3V regulator is outputting 3.9V which is out of spec. I've ordered a few more and will remove this one.

It really gets difficult keeping track of parts and separating old info due to a GDMF ^*&%^&*%&*%! computer crash.

I might need a break on this for a week or 2 and re-organize.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

I've replaced the 3.3V 5A regulator with the correct one as mentioned at the beginning of this thread. I mistakenly soldered in an older 3Amp part which must've been defective. Anyway, now measuring 3.4V on that supply. And since I had the scope out to measure the Si514 programmable oscillator, I figured I would look at all the voltage rails, 1.2V, 2.5V and 3.3V and the main 5V in. The 3.3V power rail was oscillating at about 200kHz, just like the output of the oscillator. Had a dummy moment and realized that I had forgotten to solder in the main 68uF bypass cap's for the 5Vin and the main 3.3V out from the VReg. That cleaned everything up. All voltages look clean at this point with nothing happening in the FPGA's and I'm now seeing 40MHz from the Si514 as expected.

I'll continue on working on the constraints file for the Master FPGA. I'm 3/4 done the 144 pin assignments which are mainly FPGA to SyncRAM and FPGA to FPGA. I've seen no errors yet, which is another thing to cheer about.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

Yup. Definitely worth a check.

Years ago a young fella I know was having difficulty with some troubleshooting, and I asked him whether he had scoped the power supply. He was like, why would you wanna scope the power supply? Umm... to make sure things really are as boring as you obviously assume them to be... ?

Best of luck, Sam. Have fun, and keep us posted!

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html