Are there any final changes that i should make for my design?

Thank you all for the help that you have given me along the way!

I have a suggestion or two, BigLadWhillis, although I've not spent much time with the drawing. Speaking of drawings, in future please consider posting in monochrome if possible.

A reminder about RAM chips. If it saves you any trouble -- and it might! -- feel free to exchange any address line on the RAM chip with any other address line on the RAM chip. Likewise it's alright to exchange any data line with any other data line. Yes this'll scramble what gets written, but the reverse effect occurs upon readback. This freedom to swap pins can be helpful in a physical sense, when it's time to actually make those connections.

Probably the glue logic could be collapsed somewhat, resulting in better speed potential and perhaps fewer IC's. (IDK if those are priorities for you.) Example: there are 4 gates and an inverter between A10 and RAMENABLE. One possible option is to design using 3- or 4-input AND gates, and thus have less need to cascade one gate after another.

Drogon's right about the decoupling capacitors, of course. As for pullups, the simple answer is yes, use 'em, and 3.3K is fine (although you could more than double or halve that value and still be OK).

If you're sure an input will never be used, it's OK to tie directly to Vcc. The only exception is the RDY input on a WDC CPU, where a pullup is desirable as protection in case a WAI is accidentally invoked.

In another thread,
In case you're wondering, you don't need any particular logic level if NMI is unused, or SO. IOW it's OK to hold it permanently high (or allow it to hold itself permanently high), and likewise permanently low is also OK. Unless a transition is present, these inputs won't trigger. Thus the W65C02S's internal bus holding devices are all you need. Other pins such as BE are level-sensitive, not edge-sensitive, and if unused you need to heed which way they go. IOW, don't leave them unconnected and just rely on the bus holding devices.

Have fun, and keep us posted!
Jeff

Many hours of work and browsing this forum have lead to the design of my first computer!
These are the specifications:

32k ROM
~32k RAM
256b I/O

I have included the schematic:


Are there any final changes that i should make for my design?

Thank you all for the help that you have given me along the way!

Upon examining your schematic there are some things that caught my attention. This list isn't exhaustive.

1. Ø2 clock generation. Are we looking at a can oscillator or a crystal circuit? It's not entirely clear to me.
   
   
2. Read/write. As noted by Michael, writes to the SRAM should be qualified with Ø2 so they only occur when the clock is high. During Ø2 low, the address bus and other MPU outputs are in a state of transition. RWB, according the 65C02 timing diagram, reflects the nature of the next operation (read or write) about the same time the address bus is being set up. If writing is enabled during this time there is a window of opportunity for the RAM to be exposed to a wild write before the address bus settles, which will corrupt data.
   
   
   Attachment:
   x86_read_write.gif
   
   The above circuit will work with almost any asynchronous hardware (that is, hardware that doesn't understand the 65xx bus cycle), including your RAM and ROM. Do not use it to control any 65xx peripherals.
   
   Incidentally, the ROM's /OE should be gated by /RD in the above circuit, instead of being tied to Vcc. Most ROM manufacturers state in their data sheets that using /CE only to control the ROM, as you are doing, causes a reduction in performance.
   
   
3. Memory map. Why? You won't use 32KB of ROM and probably can get by with 8KB or 12KB (I used 8KB in my POC units, and they had a full BIOS, as well as a machine language monitor in ROM). If you adapt Garth's circuit in his primer, you will have use of the entire 32KB of RAM, plus space to add more I/O once you get it going. As a bonus, you won't need so many gates.
   
   Further to this, with a change in the memory map, you could easily expose 48KB of RAM to the MPU (using a different SRAM), plus have ample space for I/O and ROM—and have no more than two gates between the address bus and any device's chip enable input. As we used to say back in the days of minicomputers with bit-sliced MPUs, memory is like money: there's no such thing as too much.
   
   
4. Ø2 clock rate. I don't want to sound discouraging, but I think your unit will be unstable at 8 MHz on account of all the cascading logic. As Jeff noted, you need to go on a logic diet.

i wasn't too fussed about the clock speed and didn't expect to be able to use 8mhz, would you say that 4mhz would be better suited?

I'm not sure I'd criticize the memory map.