Help with beginner/basic 6502 project

[TomC]

Hello all,

I've been trying to build a very simple 65C02 system as a learning project, but I must be misinterpreting or misunderstanding something.

My goal is to use a WDC 65C02 to run a program stored in a 28C256, that uses a 74HCT373 to light eight LEDs in sequence, D7 to D0 (i.e. one LED lit at a time). What I get instead is each LED lighting in sequence and staying lit.

I've attached schematics for the main portion and for the memory decode section. My apologies if they are confusing. I've omitted the LEDs, power connections, and clock as they are trivial.

Schematic notes:

1. The address bus joins the CPU to ROM via A0-A7. The upper eight lines are not used and the corresponding lines on the ROM chip are tied high, as the program is entirely contained in the highest page ($FFxx).
2. I'm cheating a bit with memory decoding by using RWB instead of A15 to determine whether the system should select ROM or the '373. My reason for doing this is because the program reads only from ROM and "writes" only to the '373.
3. CLOCK is generated by a oscillator-to-74ABT74 circuit. Frequency is 0.5 MHz.
4. RESET is controlled by a DS1813.
5. OUT_0-OUT_7 are just LEDs, each with a 470 Ω resistor.

(Btw, I'm using TTL because those were the parts I had. Further development would use 74HC logic.)

Here is the program I wrote. I used straight machine code because the code was small enough (33 bytes) to allow me to put off learning an assembler. But I've hand-assembled--accurately, I hope--the bytes into opcodes and operands:

Code: Select all

                  // Program start = $FF00
0xA9, 0x00,       // START:          LDA #00        ; clear accumulator
0x38,             //                 SEC            ; prepare carry bit.
0x6A,             // NEXT_LED:       ROR A          ; march the ant one space right
0xA0, 0x00,       // SET_Y:          LDY #00        ; inner delay loop prep
0xA2, 0x00,       // SET_X:          LDX #00        ; inner delay loop prep
0x8D, 0x00, 0x10, //                 STA $1000      ; write bit pattern to '373 and latch. Address is irrelevant
                                                    ;    since we use RWB to select the chip.
0xE8,             // NEXT_X:         INX            ; delay loop
0xF0, 0x03,       //                 BEQ NEXT_Y
0x4C, 0x0B, 0xFF, //                 JMP NEXT_X
0xC8,             // NEXT_Y:         INY
0xF0, 0x03,       //                 BEQ CHK_0
0x4C, 0x06, 0xFF, //                 JMP SET_X
0x89, 0x00,       // CHK_0           BIT #00        ; if the ant has marched all the way to the carry bit
0xF0, 0x03,       //                 BEQ NO_BLANK   ;    then restart.
0xFC, 0x03, 0xFF, //                 JMP NEXT_LED   ;    otherwise keep marching.
0xFC, 0x00, 0xFF, // NO_BLANK:       JMP START

[TomC]

My first thought was that the ROR was doing sign extension, but the WDC programming manual indicates that that's not the case. I feel like I've missed something obvious; would one of the experienced users have time to critique my work? Thanks in advance.

[Dr Jefyll]

Code: Select all

0xFC, 0x03, 0xFF, //                 JMP NEXT_LED   ;    otherwise keep marching.
0xFC, 0x00, 0xFF, // NO_BLANK:       JMP START

Hello, TomC. One thing jumped out at me, and that's these last two opcodes. Is this a transcription error that occurred when you wrote your post? Or do you really have $FC in there? The opcode for JMP abs is $4C, of course, just as you've used earlier in your code.

( $FC is undefined but is know to behave as a 3-byte NOP. So if the code really is as shown then these last two instructions do nothing, and the CPU will happily proceed to execute whatever follows -- FF's or zeroes or whatever other junk happens to be in your ROM above the intended program. )

Otherwise I've noticed no actual errors so far, although I or others may suggest improvements later.

cheers
Jeff

[Dr Jefyll]

Code: Select all

0x89, 0x00,       // CHK_0           BIT #00        ; if the ant has marched all the way to the carry bit
0xF0, 0x03,       //                 BEQ NO_BLANK   ;    then restart.

BIT # 00 will always set the zero flag. I think what you wanted was BIT #$FF. (BIT updates the zero flag according to the result of a logical AND between A and memory. You had zero in memory, so the AND result will always be zero no matter what's in A.)

BTW, using BCS or BCC is a more direct way of determining whether the ant has marched all the way to the carry bit.

Quote:

I'm cheating a bit with memory decoding by using RWB instead of A15 to determine whether the system should select ROM or the '373. My reason for doing this is because the program reads only from ROM and "writes" only to the '373.

Quick 'n dirty. I like it.

BTW your schematic shows /OE of the 373 tied high but that'd yield no LEDs, so I'm guessing it's really tied low.

[BigDumbDinosaur]

TomC wrote:

I've attached schematics for the main portion and for the memory decode section. My apologies if they are confusing. I've omitted the LEDs, power connections, and clock as they are trivial.

Please post the entire schematic...nothing is trivial when something isn't working. Also, I suggest you replace the 74ABT74 with a 74AC74 or 74AHC74. The 74ABT series generates TTL-level outputs, but if operating the 65C02 on 5 volts, a clock signal that swings between ground and Vcc (5 volts) is required.

Mixing TTL with CMOS can cause a variety of problems due to the two logic types having different logic 0 and logic 1 thresholds.

[TomC]

Dr Jefyll wrote:

Hello, TomC. One thing jumped out at me, and that's these last two opcodes. Is this a transcription error that occurred when you wrote your post? Or do you really have $FC in there? The opcode for JMP abs is $4C, of course, just as you've used earlier in your code.

I just double-checked, and I do indeed have 0xFC in those two spots--thanks for catching that. I had even hooked a cheapo 8-input logic analyzer ($20 from sparkfun) and found/ignored those two opcodes. That makes me wonder why I even got the results I did!

Dr Jefyll wrote:

BIT # 00 will always set the zero flag. I think what you wanted was BIT #$FF. (BIT updates the zero flag according to the result of a logical AND between A and memory. You had zero in memory, so the AND result will always be zero no matter what's in A.)

BTW, using BCS or BCC is a more direct way of determining whether the ant has marched all the way to the carry bit.

Thanks again--I'll review those instructions and change the program. And you're correct: the schematic is incorrect wrt /OE on the 373.

Btw, is there a way to branch backwards with BNE or BEQ?

BigDumbDinosaur wrote:

Please post the entire schematic...nothing is trivial when something isn't working. Also, I suggest you replace the 74ABT74 with a 74AC74 or 74AHC74. The 74ABT series generates TTL-level outputs, but if operating the 65C02 on 5 volts, a clock signal that swings between ground and Vcc (5 volts) is required.

Mixing TTL with CMOS can cause a variety of problems due to the two logic types having different logic 0 and logic 1 thresholds.

Sure, BDD. Here are the other 3 portions of the schematic. I'm not sure if the oscillator can symbol is correct but it is wired correctly on the breadboard.

Clock generation

PomPom_001-Clock_BW.png (2.8 KiB) Viewed 2966 times

Power

PomPom_001-Power_BW.png (2.7 KiB) Viewed 2966 times

LED output

PomPom_001-Output_BW.png (3.22 KiB) Viewed 2966 times

I see now that I forgot to include the bypass caps for the CPU and the ROM in the schematic. They are there.

As for TTL, I bought the ABT because it has the 5ns slew rate that WDC's datasheet specifies. I know about CMOS/TTL discrepancies but it was truly just a case of the parts being on hand. I made sure to apply Garth's "Murder at a Megahertz" maxim to tell myself it was ok.

(I picked up the 74HCT373 10 years ago at a rural Radio Shack that had a treasure trove of old parts. The elderly owner told me, "I just leave 'em on the shelf until they sell." He had a large inventory of tubes/valves, phonograph needles, components in the old blue Archer packaging (and some even older), several TRS-80 model IIIs...I thought I'd walked into a museum. I drove past a year ago; the building now houses a lawn care business. Sic transit)

[TomC]

Oh, wait--I see now how backward branching works. Always check the reference guide...

[GARTHWILSON]

TomC wrote:

Btw, is there a way to branch backwards with BNE or BEQ?

It's twos' complement; so if the operand's high bit is set, branching goes backwards.

[TomC]

It worked! It worked it worked it worked! :happydance:

I don't understand why it didn't work the way it did...er, didn't?...before, but changing the BIT operand and correcting the JMP instructions did the trick.

Next step will be to construct/acquire a better programmer (currently using Ben Eater's Arduino-based device on a breadboard), add a 65C22, and hang the 373 off one of the ports.

Thanks Dr J and BDD!

[BigEd]

Hurrah!

[BigDumbDinosaur]

TomC wrote:

As for TTL, I bought the ABT because it has the 5ns slew rate that WDC's datasheet specifies.

74AC hardware easily meets the 5ns slew rate, but unlike 74ABT, swings rail-to-rail. I used 74AC logic in my POC V1 series—POC V1.1 will boot at 15 MHz, so it's clear 74AC logic is sufficiently fast. POC V1.2 (currently on the drawing board) will also be 100 percent 74AC discrete logic.

Glad to read that you've got your unit working.