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PostPosted: Thu Dec 19, 2019 1:48 am 
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Hello,

I have a 65C02 based computer that I'm working on. I've posted about it before here. I've added a 65C51 ACIA to it, and I'm working on a small Hello World program to load into my ROM.

Sometimes it works great, and sometimes it doesn't. At first I thought maybe it was my crappy breadboard and loose connections, so I soldered it all up on a perfboard and I'm still having problems.

I noticed that I bought a 65C02S and a 65C51N, meaning that the 65C02 is CMOS and the 65C51 is NMOS.

Could this be what is causing my problems? Could it be that because they are different technologies they aren't behaving well together?

Thanks

PS: Please assume that my code and my circuit are perfect, I have no defective parts, and I've taken the transmit register bug into account. I just want to eliminate the mismatch of chip types from my troubleshooting at this point. The code review and circuit review can all come later.


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PostPosted: Thu Dec 19, 2019 3:06 am 
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rickseiden wrote:
I noticed that I bought a 65C02S and a 65C51N, meaning that the 65C02 is CMOS and the 65C51 is NMOS.

Could this be what is causing my problems?

The opening line of the W65C51N says, "The WDC CMOS W65C51N Asynchronous Communications Interface Adapter (ACIA) provides..." The "C" in there means it's CMOS. The N means it has an open-drain IRQ output, according to the top of page 14 of the data sheet. Can you post your code and circuit?

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PostPosted: Thu Dec 19, 2019 4:46 am 
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Open-drain IRQ means, in practical terms, that you need to provide a pull-up resistor to return the IRQ line to the quiescent state after the device de-asserts it. Otherwise it will be held low by the W65C02S' bus-holding devices, and the CPU will therefore be interrupted again as soon as the IRQ handler exits.


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PostPosted: Thu Dec 19, 2019 10:18 am 
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So it seems you have the latest WDC 65C51 part. As always, a schematic helps, but you should pay attention to the baud clock. If you're running with a can oscillator, then that should be fine. If you're using a crystal, then you have to have a 1meg resistor in parallel with it, as the latest version no longer has the 1Meg resistor on chip. To verify the clock is running, having a scope or logic analyzer would be beneficial as you can check on pin 5 for the proper clock (after setting the chip up). Beyond this, ensure you have bypass capacitors close to the chip.

In general, getting the 6551 working is pretty trivial. Here's a snippet of code that does work:

Code:
INIT_6551
;Init the 65C51
                SEI                     ;Disable Interrupts
                STZ     SIOSTAT         ;write to status reg, reset 6551
                STZ     STTVAL          ;zero status pointer
                LDX     #$02            ;Get count of 2
INIT_6551L
                LDA     LOAD_6551-1,X   ;Get Current config parameters for 6551
                STA     SIOBase+1,X     ;Write to the 6551
                DEX                     ;Decrement count
                BNE     INIT_6551L      ;Loop back until done
                CLI                     ;Re-enable Interrupts
RET             RTS                     ;Return to caller
;
CFG_TABLE       ;Configuration table for hardware devices
;
CFG_6551        ;2 bytes required for 6551
                .DB     $09             ;Default 65C51 Cmd reg, Xmit/Rcv IRQ output enabled
                .DB     $1F             ;Default 65C51 Ctl reg, (19.2K-N-8-1)
;


Note that my code copies the config data into page $03, but there's only two bytes required to setup the chip. You can also try my Micromon code for a test, which is on my github account below.

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PostPosted: Thu Dec 19, 2019 12:43 pm 
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GARTHWILSON wrote:
rickseiden wrote:
I noticed that I bought a 65C02S and a 65C51N, meaning that the 65C02 is CMOS and the 65C51 is NMOS.

Could this be what is causing my problems?

The opening line of the W65C51N says, "The WDC CMOS W65C51N Asynchronous Communications Interface Adapter (ACIA) provides..." The "C" in there means it's CMOS. The N means it has an open-drain IRQ output, according to the top of page 14 of the data sheet. Can you post your code and circuit?


Well, that right there is a classic case of RTFM! I'm sorry! The sad thing is that I have the datasheet open in my browser, and am reading it to make sure my settings for the command and control registers are correct.


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PostPosted: Thu Dec 19, 2019 12:52 pm 
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My code is pretty simple. I'm not using the interrupts at all, which I know is bad practice. I was using a timer interrupt from a VIA, but it wasn't working either, so I went with the simplest code I could come up with.

Code:
    !cpu 65c02
    !source <ACME_lib/via_defs.a>
    HELLO_TEXT=$9000
    ACIA_DATA=$5000
    ACIA_STAT=$5001
    ACIA_COMM=$5002
    ACIA_CTRL=$5003
    TX_COUNTER=$1000
 
    *=$8000
    ;+via1_a_all_out
    ;+via1_b_all_out
    sei
    lda #$00
    sta ACIA_STAT

    lda #%00001011
    sta ACIA_COMM

    lda #%00011110
    sta ACIA_CTRL

    ldx #$00

write:
;    stx VIA1_PB_PINS
    lda .hello,x
    beq end
    sta ACIA_DATA
    inx
;   ldy #$FF
;pause:
;    sty VIA1_PA_PINS
;    dey
;    bne pause
    jmp write
end:
    jmp end

    *=HELLO_TEXT
.hello !text "Hello World!",$0d, $0a, $00

    *=$FFFC
    !word $8000
    !word $FFFF


My circuit is probably too simple. I don't have the bypass caps that were mentioned, or a pullup resistor on IRQ (I've disabled interrupts in my code, so I don't think this matters at this time.)

Here's my schematic.

Attachment:
circuit.png
circuit.png [ 102.09 KiB | Viewed 1149 times ]


I have hooked up my scope to it, and it shows the Hello world! text coming through. I'm beginning to think that it's my FTDI board that could be to blame. I don't have another one to test, but I hope to be getting one soon. Maybe not an FTDI, but a CH340G based one.

The weird thing to me is that it does work sometimes, and doesn't other times. Same code running on the same circuit plugged into the same computer with the same software running. The only difference is that I'm running it at different times (not time of day, but sessions at the computer).


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PostPosted: Thu Dec 19, 2019 1:20 pm 
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If the schematic posted is accurate, there's two basic problems (beyond missing bypass caps):
1- The 27pf cap is on the wrong pin per the datasheet
2- The 1Meg resistor in parallel with the Xtal is missing per the datasheet

Also, the CPU should have a pull-up resistor connected to the IRQ line regardless... plus others, i.e., NMI, RDY, RES, BE, SO

For coding (using the current WDC part) you would need to add a delay loop to allow the chip to send the character out before writing the next character to it.

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PostPosted: Thu Dec 19, 2019 3:49 pm 
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floobydust wrote:
If the schematic posted is accurate, there's two basic problems (beyond missing bypass caps):
1- The 27pf cap is on the wrong pin per the datasheet


I put it on that pin because I was following along on this site. He had it on pin 7, so that's where I put it. I will change it.

floobydust wrote:
2- The 1Meg resistor in parallel with the Xtal is missing per the datasheet


So a 1M resistor between pins 6 and 7? I'll double check the datasheet to be sure.

floobydust wrote:
Also, the CPU should have a pull-up resistor connected to the IRQ line regardless... plus others, i.e., NMI, RDY, RES, BE, SO


I'll add the resistor to the IRQ and NMI line. I already have one on the RES line along with a button and a reset circuit connected there. BE, SO and RDY are just connected directly to 5v. I got this configuration from a Ben Eater video. I'm going to look at the data sheet for the 65C02 to see what details are there.

floobydust wrote:
For coding (using the current WDC part) you would need to add a delay loop to allow the chip to send the character out before writing the next character to it.


In the code I posted there is a delay loop, but it's commented out. I also have other code that used a VIA's Timer 1 as an interrupt to send a value to the ACIA data register instead of a delay loop. Like everything else I've done with the ACIA, sometimes it works and sometimes it doesn't.

What size capacitor would you recommend for the bypass? I'm 99% sure that I should have it connected between 5v and ground very close to the chip, but I want to ask if that's right, just in case.

Thank you for taking time to help me out!


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PostPosted: Thu Dec 19, 2019 4:27 pm 
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rickseiden wrote:
sometimes it works and sometimes it doesn't.
More detail might be helpful. When it doesn't work, are you seeing a garbled text stream? Or nothing at all, perhaps?

.01 uF or maybe .047 uF is a reasonable value for your bypass capacitors. The exact figure isn't critical. :)

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PostPosted: Thu Dec 19, 2019 4:51 pm 
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Dr Jefyll wrote:
rickseiden wrote:
sometimes it works and sometimes it doesn't.
More detail might be helpful. When it doesn't work, are you seeing a garbled text stream? Or nothing at all, perhaps?



Nothing at all. Not even flashes on the FTDI adaptor's TX and RX lines.


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PostPosted: Thu Dec 19, 2019 5:52 pm 
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floobydust wrote:
If the schematic posted is accurate, there's two basic problems...

Possibly three problems. The schematic says he's using 74LS logic. The outputs of 74LS gates cannot usually pull up to the required level to be seen as a valid logic 1 by a CMOS device, unless said device has TTL-compatible inputs—not the case with the 65C51. That the 65C51's /CS1 input is being controlled by a 74LS00 may be the problem, as the 'LS00 probably isn't pulling /CS1 high enough when the 'C51 is not supposed to be active.

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PostPosted: Thu Dec 19, 2019 6:04 pm 
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BigDumbDinosaur wrote:
floobydust wrote:
If the schematic posted is accurate, there's two basic problems...

Possibly three problems. The schematic says he's using 74LS logic. The outputs of 74LS gates cannot usually pull up to the required level to be seen as a valid logic 1 by a CMOS device, unless said device has TTL-compatible inputs—not the case with the 65C51. That the 65C51's /CS1 input is being controlled by a 74LS00 may be the problem, as the 'LS00 probably isn't pulling /CS1 high enough when the 'C51 is not supposed to be active.


Only the 04 is actually LS. The others are HC. I was just concerned with pinout when I did the schematics. I will change the 04 to HC as well when I'm updating everything, but I have tested the CS lines, and I always see the expected voltages there. Still gonna change it.....


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PostPosted: Thu Dec 19, 2019 6:42 pm 
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rickseiden wrote:
Only the 04 is actually LS. The others are HC. I was just concerned with pinout when I did the schematics. I will change the 04 to HC as well when I'm updating everything, but I have tested the CS lines, and I always see the expected voltages there. Still gonna change it.....

As a fairly general rule, you should avoid mixing basic logic types, meaning mixing TTL and CMOS devices. TTL devices generally cannot pull up to the required voltage that is recognized by a CMOS device as a logic 1. If you must use a mixed circuit use 74*CT devices for the CMOS parts. Given the general superiority of CMOS technology in terms of noise immunity and fanout, there is no good reason anymore to use 74LS in a new design. For speeds up to 8 MHz, 74HC logic will perform as needed.

Incidentally, if you are using only one section of U5 you can use the other sections of the same device as inverters and eliminate U7.5 and U8.6.

In your schematic, you give the logic equation for selecting the UART. What is the address assigned to the UART? Your selection logic seems a little complicated to me, but not knowing the expected address, I'm only guessing.

Lastly, when you post a schematic it is best to post it in black and white for the benefit of readers who have color-blindness. :D

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PostPosted: Thu Dec 19, 2019 6:50 pm 
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The logic chips are shared with addressing the ACIA and a VIA, so there are other parts of the chips used. I know that I could have run the output of the final and gate through the inverter, but I wanted the nand gate in there to make it easier for me to understand.

The ACIA is addressed at $5000-$5FFF. I have two VIAs addressed at $6000-$6FFF and $7000-$7FFF. My ROM is $8000-$FFFF. My RAM is $0000-$3FFF.

I hadn't thought about the color/color blind issue. It's a good point. I'll keep it in mind for the future. Thanks.


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PostPosted: Thu Dec 19, 2019 7:32 pm 
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Be sure to go through the 6502 primer at http://wilsonminesco.com/6502primer/ . I can think of quite a few possible causes of your problems, but I wouldn't give any individual one a very high chance of being the key until I know more about your system. The 6502 primer should address all of them though.

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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?


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