Hello,

Two quick questions.

Does the W65C51 have to be running at 1 megahertz or faster to properly function, or can it operate at lower frequencies like the W65C02 can?

In my internet searches trying to get my W65C51 working, I've come across some really old posts that talk about a bug with the chip related to the transmit flag. It says you aren't supposed to read the status register, but instead build in a delay to let the chip finish transmitting. These posts are 6 years old, so I'm wondering if the bug still exists, or if my newer W65C51 should work without it.

Thanks
Rick

The bug is still there. Doing a software loop delay for it is a pretty poor way to handle it though IMO. Forum member GaBuZoMeu has the best solution yet: Use the 51's pin 5 (if in DIP), the x16 clock, as an output to drive a VIA's PB6 for its T2 to count pulses and generate an interrupt. The T2 latch value does not need to change with Φ2 rate nor with baud rate.

Edit: Also, according to the data sheet, there's no minimum phase-2 rate for the W65C51N or W65C51S.

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What's an additional VIA among friends, anyhow?

All presently-produced WDC products are fully static. It's possible to stop the Ø2 clock and have the device registers hold their contents. That said, halting the clock while the UART is processing data would not be a good idea.


As Garth noted, the bug remains in current production 65C51s. The problem is the TxD ready bit is always set, making it appear the transmitter is ready for another datum, even when it isn't. Furthermore, one cannot enable TxD ready IRQs, as the 65C51 will continuously interrupt the MPU, causing the system to go into deadlock. As TxD in the 65C51 is a one deep register, writing something to it while it is serializing the previous datum will result in corruption. So this device is quite crippled.

The timer IRQ method of pacing the transmitter is the only really workable solution at this time. It's been some six years since this bug was identified and to date, all that WDC has done is put a note in the data sheet telling us not to use TxD ready and find some other way of pacing the transmitter. I imply that to mean the bug is unlikely to ever be fixed. Better to use a modern UART design.

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On the 816SXB i used one of the 65C22 timers set to the character transmission time to generate an interrupt and used that to trigger reloading the ACIA transmit buffer.

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Andrew Jacobs
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