Flexible clock circuit

[GaBuZoMeu]

Thanks Garth!

I could extract this page:

relaxation_osc.pdf

(147.19 KiB) Downloaded 69 times

If I'm not too drowsy then 1MOhm x 1uF would yield 1 s.

If using a (trim)pot for R use an additional resistor (e.g. 1K or more) in series with the pot as a sort of safeguard (just don't short output to input).


Regards

[BigEd]

GARTHWILSON wrote:

I was going to post links to NSC (later Fairchild) ap. notes, but when ON Semi took over Fairchild, they wiped them out. I've been able to get them to re-post some of them, and now I just sent another email asking for these two, which I have old links to on my 6502 primer's clock-generation page and just realized I still need updated links to:

HCMOS crystal oscillators (AN-340) and
CMOS oscillators (AN-118)

I have them on paper but unfortunately not in electronic form to attach here. I plan to update this (as well as the links on my website) when I hear back from ON Semi.

Internet Archive to the rescue - there are links to archived versions of the app notes from archived versions of your webpage.

[GARTHWILSON]

Thanks, Ed. I still need to tune my thinking to more quickly go to archive.org when something is gone. In this case of course it's not my web page (we back up the whole site a couple of times a day anyway), but rather the ap. notes.

So here's one: https://web.archive.org/web/20180311021 ... AN-340.pdf

Here's the other: https://web.archive.org/web/20170904003 ... AN-118.pdf

I just now made the links on the page point to these on archive.org.

[joanlluch]

GaBuZoMeu wrote:

Thanks Garth!

I could extract this page:

relaxation_osc.pdf

If I'm not too drowsy then 1MOhm x 1uF would yield 1 s.

If using a (trim)pot for R use an additional resistor (e.g. 1K or more) in series with the pot as a sort of safeguard (just don't short output to input).


Regards

I would still need an edge triggered J-K flip flop after that to obtain a proper 50% duty cycle (half frequency) signal, is this right?

Thanks

[GARTHWILSON]

joanlluch wrote:

I would still need an edge triggered J-K flip flop after that to obtain a proper 50% duty cycle (half frequency) signal, is this right?

What's important is meeting the timing requirements in the data sheet. WDC's 65c02 has only a minimum number of nanoseconds for each half of the cycle, whereas Rockwell's and others also have a maximum Φ2-low time. The latter is the reason for the fifth diagram on the 6502 primer's clock-generation page which allows you single cycle one of these other brands by using a pushbutton. Obviously then this will provide a horrendously asymmetrical waveform, to keep the processor from failing at these ultra-low frequencies. As long as you're within the timing specifications, symmetry does not matter. You only need the symmetry if you're pushing the upper speed limit; and even then, I suspect that if you had a way to experiment and microadjust the Φ2-high and Φ2-low times independently of each other to find the maximum possible operating speed, you'd find they're not exactly equal. Without a way to do that, symmetry is your friend for maximum operating speed. For now, you seem to be interested in 10Hz and down, so don't worry about symmetry.

[GaBuZoMeu]

joanlluch wrote:

I would still need an edge triggered J-K flip flop after that to obtain a proper 50% duty cycle (half frequency) signal, is this right?

Thanks

You may do so if you feel more comfortable with a symmetrical clock.

Instead of a J-K FF I would choose a D-FF (with /Q wired to D) but that is only a personal preference.

If you wish to run your circuitry with less than 1 Hz, say 1/10 Hz or even 1/100 Hz you can use a binary counter like a 74HC4040 and choose one of its twelve outputs each at 1/2 speed of its preceding one and each truly symmetrical. Just take a look at page 5 of the datasheet.

[1024MAK]

The 74HC4060 (datasheet) is handy for slow clocks, as it has an oscillator circuit and dividers all in one chip

The oscillator can either be a RC type or a crystal type.

Mark