Greetings all, I recently bought a 1978 PET 2001 with the chiclet keyboard. I've cleaned and tested the power supply and all is well, however, on power up, I get a constantly running tape deck and a bright horizontal line on the VDU.

Now the tape deck issue is probably boot related, but for now I need to solve the horizontal line.

I've tested the video output connector and I'm seeing a healthy sync pulse on the horizontal pin, at the correct frequency and voltage, but a plain old noisy 4-5VDC on the vertical pin. So the board isn't supplying vertical sync. And here's where my basic experience falls a bit flat. I can trace the signal back but I'm not really sure where the sync is generated and what happens on the various logic gates it goes through. All I can do at the moment is look at measure continuity and voltages.

Is anyone knowledgeable enough to guide me through the board, so I know what I'm looking for? I've attached some images for assistance. Please ignore the frequency reading on the vertical sync image, it's just noise.

To add, on chip D8 (SN74LS00N), which is the last IC before the vertical sync, I'm getting

pin 1 = 3.97V
pin 2 = 0.16V
pin 3 = 4.46V
pin 4 = 4.46V
pin 5 = 4.46V
pin 6 = 0V
pin 7 = 0V
pin 8 = 1.78V
pin 9 = 1.94V
pin 10 = 1.46V
pin 11 = 4.46V
pin 12 = 0V
pin 13 = 4.3V
pin 14 = 5V

On chip B6 (74LS107N), the next IC along, I get:

pin 1 = 0V
pin 2 = 4.3V
pin 3 = 4.46V
pin 4 = 4.4V
pin 5 = 4.4V
pin 6 and 7 = 0V
pin 8 = 4.46V
pin 9 = 0V
pin 10 = 5V
pin 11 = 4.3V
pin 12 = 0V
pin 13 and 14 = 5V

None of the pins show a waveform, so my suspicion is that these two ICs are ok and the issue is further back in the chain.

I went down to A1 (74LS93) which has slightly rusty legs on my board but appears otherwise ok (I had to scratch the legs a little to get a signal). This is a divide by 2/4/8 counter and looks to be taking the signal on pin 1 and sending it to one of the ROM chips. It seems to be doing its job correctly (although I'm not sure what's expected on inputs 2 & 3) so I'll move over to C7. The output from C7 feeds this chip (A1) and B6, and so far appears to be permanently low.

1 - 16.556KHz 60µs at 3.48V - this appears to be a clock input from D5 (74LS107)
2 - 0.16V
3 - 5.11V
4 - 0V - pin not connected
5 - 5.11V - power rail
6 - 0V - pin not connected
7 - 0V - pin not connected
8 - 3.906KHz 256µs at 3V - output to A2 6540 and B1 74LS20 and E8 74LS04
9 - 7.812KHz 128µs at 2.92V - output to A2 6540 B1 74LS20
10 - 0V - ground
11 - 1.953KHz 512µs at 3V - output to A2 6540, B1 74LS20 and E8 74LS04
12 - 0.08V
13 - 0V - pin not connected
14 - 4.05V

Hi, and welcome to the forum.
I'm not familiar with the innards of the PET 2001, but let's make a try.

So it's PET 2001, not PET 2001N.

D8 (74LS00) output pin 11 (VERT_DRIVE) always is high, because D8 pin 12 always is low.
D8 pin 12 is fed by the B6 (74LS107) flipflops, which do nothing because their clock inputs pin 9 and pin 12 are stuck low.
Clock for B6 pin 9 and pin 12 is generated by C7 (74LS107) output pin 3, the clock signal also is supposed to be at testpoint TP3-3 and A1 (74LS93) pin 2.


The question is, why is C7 (74LS107) output pin 3 stuck low ?

C7 (74LS107) pin 4 (K) and pin 13 (/CLR) is supposed to be high, testpoint TP3-2.
C7 pin 12 (CLK) is supposed to get a 1MHz clock signal from C9 (74LS93) output pin 8.

There is supposed to be a signal at C7 pin 1 (J) generated by C6 (74LS08) output pin 11,
if there is no signal, what's at C6 pin 12 and pin 13 ?

Thanks for the reply, I'm currently working my way down through the circuit. Just spent 30 minutes trying to discover why I couldn't find a short between two chips only to realise that I think the circuit I'm working from is mis-labelling D8 (on my board it's D7, verified by measuring from the video connector straight to the chip). I'm pretty sure they've mislabelled E8 too. But I can easily follow the connections with my meter.

I was actually in the process of looking back at D8 (as labelled on the circuit diag) and had checked the E5 invertor on pins 10 and 11 (which works), so it looks like you've pointed me in the correct direction.

/edit:

Will measure the values you've requested and get back to you.

I've measured the following:

C7 (74LS107):

pin 1 - 0V
pin 2 - 5.1V
pin 3 - 0.08V
pin 4 - 5.1V
pin 5 - 15.625K 64µs 3.08V
pin 6 - same as 5
pin 7 - 0V
pin 8 - 5.11V
pin 9 - 31.312K 31µs 3V
pin 10 - 5.1V
pin 11 - 5.1V
pin 12 - unstable 1.8V - 2.1V
pin 13 - 5.1V
pin 14 - 5.1V

I will go back now and measure C7 and C9

Sorry to hear, that the labelling on the board and the labelling in the schematic is different, this sure limits the fun.

Might be, that one of the old TTL chips is dead.
If this is the case, it might be getting more warm than the others.
If you notice a too hot TTL chip by accident, maybe we should take a closer look at it.

Edit:
C7 (74LS107) pin 1 (J) is low, so let's take a look at C6 pin 11,12,13.

Yeah I'm not the only one, I've read another post on another forum (perhaps this one, I lose count) where someone noticed the same thing. It doesn't affect things though, if in doubt I just check for continuity.

Ok so C9 pin 8 is the same unstable signal as on C7 pin 12.

C6:

pin 11 - 0.08V
pin 12 - 0.08V
pin 13 - 15.625KHz 64µs 2.59Vrms (about 4.7p-p) - I've attached a pic of this.

/edit - see correction below

We need to find out, why C6 (74LS08) input pin 12 is stuck low.

Check C6 (74LS08) pin 2 and pin 4, C5 (74LS107) pin 8..pin 11.

So c6 pin 12 is holding the output low. I will measure c5. Nothing appears hot btw, apart from the rom and ram chips which are currently heating the house...

So on C6 I measure:

pin 2 - 31.5KHz (may not be completely accurate, the scope is only cheap), 31µs, 3Vrms
pin 3 - 15.625KHz, 64µs, 2.19Vrms
pin 4 - 15.625KHz, 64µs, 3Vrms

and on C5 (I measured them all as I think it's useful for people with similar problems to have something to compare to)

pin 1 - 15.625KHz, 64µs, 3.32Vrms
pin 2 - 15.625KHz, 64µs, 2.35Vrms
pin 3 - 0V
pin 4 - 15.625KHz, 64µs, 2.59Vrms
pin 5 - 15.625KHz, 64µs, 3.4Vrms
pin 6 - 15.625KHz, 64µs, 2.67Vrms
pin 7 = 0V ground (haven't checked but I'm presuming)
pin 8 - 31-32KHz, 30µs, 2.1Vrms - this has an odd double peak I haven't seen on the board so I've attached a pic of this. The scope was struggling to read the frequency because of this.
pin 9 - unstable 0.5-3V
pin 10 - 5.1V
pin 11 - slightly jittery 15.625KHz, 64µs, 2.1Vrms
pin 12 - 126.992KHz, 7.8µs, 2.83Vrms
pin 13 - 5.1V
pin 14 - 5.1V

C5 (74LS107) output pin 6 (/Q): 15.625kHz.
C6 (74LS08) input pin 12: 0.08V which means low.

In the schematic, C5 pin 6 is connected to C6 pin 12.
An unconnected TTL input pin is supposed to have more than 0.08V.

Either I have the wrong schematic, or something certainly went wrong with the labelling of the chips.
Running out of time now, I'll back tomorrow.

Thanks very much for your help, I just noticed that too. I'm eating but I'll measure it within the hour, perhaps I didn't have a good connection on the pin.

/edit - ok just checked, apologies it's my scruffy handwriting. I got 12 and 13 mixed up. The correct C6 values are:

pin 11 - 0.08V
pin 12 - 15.625KHz 64µs 2.59Vrms (about 4.7p-p) - I've attached a pic of this.
pin 13 - 0.08V

pin 13 goes back to D8 output pin 6. Gonna have a cup of tea.

Checked the schematic-labelled E8 (74LS20) - which confusingly should be E7 on my board, if I'm counting from the memory expansion edge connector). There is an identical 74LS20 nearer the regulators but I can't see it on the schematic.

I've confirmed that I'm on the correct chip by measuring continuity between that and D8 (again, D7 on my board and connected directly to the vertical pin on the video connector).

E8:

pin 1 - 0.08V
pin 2 - 0.08V
pin 3 - 0V
pin 4 - 0V
pin 5 - 0V
pin 6 - 4.46V
pin 7 - 0V ground
pin 8 - 4.46V
pin 9 - 5.1V
pin 10 - 0V
pin 11 - 0V
pin 12 - 3.32V
pin 13 - 0.8V
pin 14 - 5.1V

My current understanding is that I need pin 6 of D8 to be high, but as it's a NOR gate and both inputs from pins 4 and 5 are high, it's going to stay low. I need 4 & 5 on D8 to be low.

Ok I'm getting a bit confused now because the schematic:

http://zimmers.net/anonftp/pub/cbm/sche ... 0008-3.gif

...shows D8 4,5 and 6 as a NOR gate, but the 74LS00 datasheet has it as containing 4 NAND gates. I wonder if this is a mistake on the schematic.