In the first case, the IR isn't getting a BRK instruction inserted into it at first, but it
is going through the timing of an interrupt sequence. So the LDA# logic is firing for all those cycles, hence moving whatever's on the data bus into A.
Hard to understand exactly what's going on in the second case, but the T0+T1 state is new to me, and seems to be responsible for the wacky PC behaviour.
(This all came about after watching the recent
Ben Eater video on building a 6502 based computer, where he showed the 6502 reset sequence briefly setting the address bus to FFFF. Why's that? I thought. Well...)