If the chips are plugged into sockets, it would be worth to check for bad contact or corrosion.
If the chips are soldered directly into the PCB, then ripping IC1\IC2\IC4 out of a functional organ for plugging them into the PCB won't be an option.
Is it a brownish PCB (phenolic paper FR1 or FR2), or is it a greenish PCB (FR4 epoxy) ?
If it's a phenolic paper PCB, I would suggest to take a closer look at it if there are hairline cracks somewhere.
It also would be a good idea to check for bad solder joints.
//Had my share of PCB hairline cracks and bad solder joints when I did TV repairs for a living in the 90s.
I suppose, that the +5V are nice and clean (no ripple from a dried out electrolytic capacitor in the power supply).
/IC, low_active initial clear generated by IC30, is the reset signal for the master CPU, IC1 pin 29.
It is supposed to stay low for a short moment after power on.
IC29, IC51 generate a 6.4MHz master clock labeled 'PHI2', but that clock signal doesn't seem to drive clock inputs of IC1\IC2\IC4, so we can ignore it for now.
The 2MHz clock is there (generated from IC1 pin 40), so the 8MHz crystal at IC1 is supposed to be oscillating.
The 125kHz clock is there, I would say IC13 generates it on pin 14 by dividing the 2MHz clock by 16.
Does the 8MHz crystal at the slave CPU IC2 pin 2, pin 3 oscillate ?
The 125kHz clock is buffered by an OR gate (IC31) before it leaves the PCB, are the 125kHz present at IC31 output pin 6 ?
IC3 YM2154 rythm generator, is the 2.7MHz crystal at IC3 pin 63 and pin 64 oscillating ?
When the master CPU IC1 is stuck in a loop, does it try to communicate with the slave CPU IC2 ?
If yes, there would be spikes at IC2 pin 21 and/or pin 22, generated by the IC4 gate array.
IC11, the RAM for the master CPU. What's the VCC voltage at pin 28 of the RAM ?
A supercap for preventing the RAM contents from getting lost during power off, that's nice. //No acid leaking out of batteries.
Also, a 74LS03 open collector NAND prevents the RAM /CS from getting active at power on (by making use of the /IC signal)
for preventing incorrect/accidental RAM writes by a master CPU which has entered reset condition at power on a little bit too late.
Are there spikes at IC11 pin 20 /CE ?
If the master CPU reads the ROM, then there are spikes supposed to be at the low_active enable inputs pin1 and pin 19 of the IC27 bus buffer (74HC244).
If the list above won't provide any clues about the problem, then we need to dig a bit deeper.
An internet search for "Yamaha HS-5 reverse engineering" brought no results so far.