So after almost five years, I resumed that old idea of mine to play with an old NMOS 6502 I found on a 1541 (timecode 3084, pretty much my age ). See viewtopic.php?f=4&t=3102

I'm starting with some basic tests. I'm sending a 5V 100kHz clock signal to pin 37, and expecting Phi1 and Phi2 (pins 3 and 39 respectively) to return the same signal (inverted on Phi2). But to my surprise, I get a "high" voltage of 1V and a low of 0.4V.

I suppose that part of the chip is unaffected by anything else, so I can't say what did go wrong. Is my 6502 dead?

Kind regards,
Enrico

Is there something that could be loading it down? NMOS cannot pull up very hard like CMOS can. Otherwise, yeah, it sounds damaged.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

What was the scope probe setting? 10:1 would be ok, 1:1 is a little load - allthough 100 KHz isn't much. Did you try 1 MHz? (There is a minimum frequency requirement when operating the 6502, but I would not assume that the oscillator section is part of that limitation.)

Have you verified that it really is a 5V signal (while pin 37 is connected, I mean)? Better check, if you haven't already. Also, you're using a 5V supply for Vdd, right? (Check that, too. I would do the same myself.)

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

No, nothing else on the breadboard is connected to those two pins.


The clock comes from an Arduino Due, I level-convert it from 3.3V to 5V before feeding to Phi0, and both voltages are OK without changing settings to the scope.


Yes and yes (4.67V actually, iirc). The only issue I found is an unusually high rise time, lasting around 1us over a 5us high pulse, due to the level converter. Is that an issue?

A 1µs rise time to CMOS levels would be normal for 74LS series logic, which uses TTL levels normally. It would be abnormal for 74HCT series logic which you could sensibly use as a 3.3V-5V level shifter (but not the other way around).

Check your 5V power supply. Is it at the correct voltage, and how much current is being drawn on it?

Um... right. I agree a 74HCT series inverter or gate would be appropriate as a level shifter. It can be powered by the same +5V supply as the 6502.

The level shifter you're presently using is not satisfactory for driving a clock input -- 1 uS is too slow; the 6502 can't operate properly with this. I hesitate to say it would actually squelch the output on pins 3 and 39, but it might. In other words, try a better level shifter. Only then will we know whether or not your 6502 is defective.

( 74HCT is preferred, but you also can use a 74LS series gate or inverter if a low-value pullup resistor is attached from its output to +5. I'd try 1k, or maybe 470 ohms or less. )

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

And did you properly bypass all Vcc's and Vdd's for each participant?

I replaced the Due + level shifter with a Uno, that can provide a 5V clock. No noticeable change.
I didn't add bypass capacitors. Are they that important for such a basic test?

If your Vdd isn't stable there can happen weird things. Just give it a try .

Right. The caps do have a function. And you have an experiment that's failing. Why hesitate?


Does it yield satisfactory rise and fall times for the clock signal applied to pin 37? They should be 10 ns or less, according to the R6502 datasheet I have here.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Trying with bypass capacitors helped me find out the actual problem. I realized I connected my 5V to pin 7 (SYNC) instead of 8 (Vdd). Now the clocks are working fine.

Thank you all for the help!

Congratulation