6502 was fabbed in 8um process. Now, we are at around 10nm process. 6502 was more or less a square of 4mm, it could be reduced to around 4um, if a simple linear scaling is assumed. It doesn`t need to have the same layout and also you could enormously spread the transistors and interconnectors for better cooling, like, passing water or liquid nitrogen or helium between the components.

Welcome. Don't forget the space needed for bonding the wires that connect the die to the lead frame. These pads would dwarf the actual processor area. Current production for off-the-shelf 65c02's is at 0.6µm. Bill Mensch said in an interview a couple of years ago that he estimated that with the newest (for the time) small die feature size, the '02 would run at 10GHz. I suspect silicon physics other than size would keep it from ever going much above that though. I could be wrong about that. Regardless, memory, I/O, and other support would all have to be on the same die, since running buses outboard would be limited to a fraction of that speed. For many years, there have been 65c02's being produced this way that are running over 200MHz in ASICs, according to WDC, the IP holder and licenser.

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Thank you for the welcome!

So, what you mentioned that 10GHz could be done according to Bill Mensch. I think that supposes more or less a linear scaling, right? If that is the case, it would not be a simple scaling, as I mentioned. The die and the silicon would have liquid cooling passing through the components. This chip is small enough that I think you can cut trough it with small chanels. Or, equivalentely, build the components so far away, relative to their size, that small channels could be cut. The other parts of the circuit would be similarly scaled down, if needed.

It's an interesting curiosity (for me, maybe) making these lovely old chips run fast - I ask 'why?' when there are better/modern solutions for higher speed embedded microcontroller type applications, although I'm as guilty as the next, running my 6502 and 65816 boards at 16Mhz (ok, only 2Mhz faster than the rated 14, but...)

However if you want fast, then there is a software emulation of the 6502 that runs at a shade under 300Mhz, complete with 64K RAM that runs inside a 1Ghz Raspberry Pi Zero - this would obviously be much faster in a Piv4, or even a modern x86 system. could you get to 1GHz with a 3-4Ghz x86 type system? I don't know. The downside of these types of systems is external bus type access - which is very possible with an FPGA type solution.

-Gordon

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--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

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http://WilsonMinesCo.com/ lots of 6502 resources
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I really don`t know how I`d do it. It`s not that I have the money to test anything. But, what I surprised it is that these old circuits should be more of a target to overclocking records. A 6502 in a 7nm should measure something have an area of 15 micrometer2. A very fast current could be used to cool it down, maybe?

Reminds me of Hillary's response when asked why anyone would want to climb Mt. Everest.

The one thing the 65xx family has going for it is accessibility, with an easily-understood assembly language. That, it would seem, is more than enough reason to see just how fast a 65xx-based device can be run.

As far as getting a 65C02 or 65C816 into the gigahertz range, be careful what you wish for. Overall system design becomes more than a little complicated even at relatively modest speeds of 30 or 50 MHz. I shudder to think about what it would take to support a 1 GHz MPU of any type.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

While it's true that headline geometries are ever-shrinking, it's also true that the costs of design and tooling are exponentially increasing. The cheapest chips are not made on the latest processes! Last I looked, 350nm (0.35u) was a good tradeoff of cost vs density.

See this teardown of a 3 cent microcontroller for orientation:
https://electronupdate.blogspot.com/201 ... aduak.html

It's quite true that power density has become the limiting factor, and active cooling is part of the answer. When were just about pushing 2GHz in the consumer space, the tradeoffs were all about performance, or rather clock speed, and never mind the inefficiency.

The various measures one might use when embarking on a project would be
compute power per unit of area
compute power per dollar
compute power per watt
and these different measures lead to different tradeoffs.

Because of the non-linear increase of power (therefore heat) with clock speed, and the decreasing efficiency of raising clock speed (because every flop has a setup time to meet, and a clock-to-Q time, and the faster the clock goes, the fewer useful logic gates you can fit between flops) the fastest production chip runs at 5.5GHz - not 10GHz!

For info on costs increasing as process geometry shrinks, see for example
https://anysilicon.com/semiconductor-wafer-mask-costs/
https://www.techdesignforums.com/practi ... ansitions/
https://www.extremetech.com/computing/2 ... ocess-node


(The slow path in a 6502 is probably the 16-bit bit incrementer for the PC, which has some lookahead, and does not have a full cycle to complete. If you wanted to make a superfast CPU for some reason, with the limitation being an 8 bit ALU and a 16 bit incrementer, it probably wouldn't look like a 6502.)

A good deal of the complication in "modern" CPUs - meaning anything from about 1990 onwards - is simply interfacing an increasingly fast CPU core to considerably less fast memories and I/O devices. With early microprocessors like the 6502, the memory was actually faster than the CPU and so could be pressed into double duty, feeding a video display as well as the CPU without slowing the latter down. But that hasn't been true for a long time now.

It's well worth remembering that a light-nanosecond is roughly a foot, so the observability horizon per clock cycle at 100GHz is about 3mm. In practice this means it's physically impossible to build a complete computer at that speed with single-cycle latency if it's physically more than 1mm across, because electric signals in practical wires travel more slowly than light in free space, and signals generally have to get both from the CPU to memory and back again within the limit. Even at today's practical speeds in the vicinity of 4GHz, pipelining and caching is needed just to get signals physically across the die and then the motherboard to the RAM.

Intel promised, once upon a time, that we would have 10GHz CPUs by now. That was before they ran into the (firebrick) wall with the Prescott version of the Pentium 4. I don't believe 10GHz will ever happen, myself; instead we will see more work being done per cycle, at about the same clock speeds as today. In that context the 6502 is not a good fit for the future, even if it could be made to run extremely fast; its fastest instructions take 2 cycles, whereas many modern CPUs can execute 4 instructions per cycle per core, and each such instruction does more than anything the 6502 has.

The big advantages of the 6502 are in its friendliness to hobbyists: ludicrously simple and flexible systems design that allows for hand building with only minor skill, programming techniques that are reasonably easy to learn and work with, and interrupt latencies that are very low compared to most alternatives.

It is somewhat interesting that an emulated 6502 on a cheap ARM can run faster than an implementation on a reasonably priced FPGA. That's the scaling power of high volume manufacturing, in part, and in part it's about the effectiveness of custom silicon.

(It's also notable that an instruction-accurate emulation of a 6502 core alone is likely to run at least 10x faster than a cycle-accurate emulation of an 8-bit machine. Dealing with the intricacies of the interactions of three or four complex chips turns out to be costly.)

How expensive would it be tape out a 6502 in 7nm? A chip would be smaller than a red blood cell and a 300mm wafer would yield over 15 billion dice.

I'm not sure, but I don't think you'd step-and-repeat a tiny die so many times. I imagine you'd make a mask with a large number of die in an array. At which point, your mask costs are like anyone else's - at least in the millions, perhaps the tens of millions. Could you get anyone to make a tiny mask? How much would they charge? And could you convince a fab to step-and-repeat so many times? It would slow down production, which means huge opportunity costs.

(It's possible my idea of how things work is out of date or just plain wrong. But I'm not sure how many experts you'll reach here.)

Perhaps a normal mask, with, say 1 million chips, living the remaining blank? I think this would cost much less. 1 million chips is a tiny speck in a 300mm wafer.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?