Hi there!

I am hoping that someone here with more experience will be able to help me with my first SBC...it isn't working, and I am at my wits end trying to figure out what is going on with it.

First, here's the schematic:

Eagle schematic: http://ccureau.googlepages.com/mainboard.sch
PDF version: http://ccureau.googlepages.com/mainboard.pdf
Postscript version: http://ccureau.googlepages.com/mainboard.ps

Parts list:

CPU: WDC 65c02
ACIA: WDC 65c51
RAM: 2 pieces Toshiba TC55328P-35
ROM: Catalyst CAT28Cc64BG-90
Maxim MAX233
All TTL is HC or HCT technology

I've built it according to the specification on a breadboard, but so far I've not been able to get the thing to work. My ROM is burned with a short program from elsewhere on 6502.org which prompts for an xmodem transfer, then loads that image into memory and executes it. When I apply power, I get absolutely nothing out of the board. :-\

I don't have an oscilloscope, but I am able to test voltages with a DMM. I've single stepped the processor through NOP instructions, and it seems to work fine. I am really not sure what could be wrong, and I would appreciate any helpful hints that anyone has to try to figure this out.

Thanks,
Chris Cureau

Hi Chris,

I'm still trying to wade through the schematic. Can you help?

What is the address decoding scheme you are trying to accomplish?

I can decipher this:
$E000 - $FFFF ROM
$C000 - $DFFF ACIA
$8000 - $BFFF RAM 2
$0000 - $7FFF RAM 1

I think you have over complicated the decoding.

Also, you will want to AND the /WE pins with PHI2 on the memory to prevent false writes.

Let us know so we can help simplify the decoding.

Daryl

Hi, Daryl!

Yes, I know...I was posting in a hurry and didn't give a very good description. Here's the memory map I had hoped for:

$0000 - $7FFF = 1st 32k RAM
$8000 - $BFFF = 2nd 32k RAM (only 16k used right now)
$C000 - $DFFF = I/O mapping area (explained below)
$E000 - $FFFF = 8k ROM

The first '138 splits the entire memory into 8k chunks, and pin Y7 is used to activate the ROM. Pin 6 from the first '138 is fed into the second '138 to provide 1k blocks for I/O devices. The ACIA should reside at $DC00

I'll be happy to answer any questions, and I'll try to post more tomorrow when I have more time....sorry about that!

OK Chris,

I would change IC4's inputs to:

A = A10
B = A11
C= A12

G1 = +5
G2A = /Y6 (you can remove the inverter)
G2B = Gnd

This will allow IC4 to decode 1k blocks from
$C000 - $DFFF

You can keep Y7 from IC1 going to the ROM /CE.
And Y7 from IC4 still goes to the ACIA.

Your RAM 2 /CS logic is too complex. You can remove IC5 completely as its not doing anything (as written). You don't need to use IC1 or IC4 to decode RAM 2.

You can just NAND A15 and /A14 (inverted A14) and connect that to RAM 2 /CE.

You can then drop IC5 & IC9 and add 1 quad 2 input NAND (74LS00).
IC6A, 6B, & 6C are freed up - use one for the inverted A14.

Again, I would NAND PHI2 and inverted R/W and connect that to the /WE pins of your memory.

One last note, if you intend to write to the EEPROM, only do it from code running in RAM. The write cycle is too long and if your code is in the EEPROM, your CPU will fetch bogus data as soon as you write to EEPROM. (I learned that the hard way).

Good luck. This is alway the best way to learn. Keep on building!!!

Daryl

Actually, you can do away with IC6 too and use the spare NAND gates as the inverters.

1/4 NAND = inverter for R/W
1/4 NAND = inverter for A14
1/4 NAND = PHI2 + inverted R/W -> to /WE pins
1/4 NAND = A15 + inverted A14 -> RAM 2 /CE

Daryl

I haven't spent a lot of time looking at the details, but wow you have a lot of gate-delay levels!! What's the clock speed and the memory speed? Be sure to pay attention to what 8-bit is saying about false writes in the RAM. The RAM must not be allowed to write when phase 2 is low.

See my debugging tips starting at viewtopic.php?t=342&start=35 (in the third page of my "Tip of the Day" column).

Hi chris,

I checked your PDF schematic and I can't make sense of the reset circuit.
Are you sure you didn't have this in mind?

_________________
I trust my somewhat flawed English is comprehensible to all.

Thanks very much to everyone for their suggestions! As you can probably tell, this is my first hardware project, and it is very much a learning process. I'm glad that there are so many active and helpful members here.

I'll try to answer everyone in order:

Daryl: fitting each I/O area into 8 128 byte areas is much nicer than the 1k blocks...I had been in a hurry just to get something working and didn't pay much attention to the refinements. I need to try to understand your logic suggestions, but drawing it out will help me with that. Thanks a lot for your suggestions!

Garth: I won't be writing to the EEPROM at this stage, so I could just tie /WE high. I had done that on my original schematic (it's gone through a lot of revisions already) but decided to go ahead and connect it to the R/W bus in preparation for the future. The RAM speed is 35ns and the ROM is 90ns -- I was a bit worried about the ROM, but I think it'll work. Right now, the board is going to run at 1MHz, but I'd like to get it going at least 4MHz (10MHz would be wonderful!) in the future. I'll probably have to change out the ROM at some point...

Raccoon: Actually, I hadn't updated that portion of my schematic...you are right about the reset circuit. I've actually put a DS1501Y onto the board and used that for the reset circuit. Again, planning for the future...I want a RTC on the board as well.

Thanks again, and I'll keep you all informed!

This is the decoder section as I described it:



hope that helps!

Daryl