Hello,
I am starting this thread to introduce the 65A24, a fictitious "software only" member of the 65-series family that extends the 6502 to full 24-bit addressing with 32 bit registers. The goal of the 65A24 is to improve on the 65816 by removing kludgy features like memory segmentation, reliance on bank 0 memory for important things like vectors, the stack, direct page, etc. and adding extra features to improve ease of use and programmability.
Since I don't have a great deal of documentation on this system yet, I will introduce aspects of it little by little to the community. First I would like to talk about the registers:
Accumulator: Full 32 bits
"B" register: Full 32 bits
"X" index register: 24 bits
"Y" index register: 24 bits
"S" stack pointer: 24 bits, which allows the stack to be located anywhere in 16 megs of memory
"P" processor status register - lowest 8 bits are the legacy 6502 flags, with an extra 16 flags to control new features of the 65A24.
"m" and "x" bits of the 65816 flags register have been removed, and now there are two "am" bits which control the width of the A/B registers. Two "xy" bits in the PSR control the width of the X and Y registers. They are set/reset with the SEP and REP operations which now take a 24 bit immediate operand. They can also be set with the following operations:
AMB, AMW, AMA, AML, XYB, XYW, XYA
These set the am and xy bits to "byte length", "word length", "address length" (24 bits), or "long length" (32 bits). Obviously there is no XYL instruction and xy bits in the PSR set to a 32 bit length would be meaningless, at least for now.
For example, the code:
AML
LDA #$deadbeef
would assemble to: F3 A9 EF BE AD DE.
The 65816's XBA instruction has been retained, which allows swapping between the accumulator and the shadow "B" register which sits behind it.
All of the 65816's Long absolute, long absolute indexed, long indirect, etc. addressing modes have been removed because they are unnecessary - ALL addresses are long now, except for direct page addresses which are still one byte in length and index into the 256 byte direct page which can now be located anywhere in memory. For instance, the following code relocates the direct page to the 256 byte region beginning at $e92000:
AMA
LDA #$e92000
TCD
(or PHA, PLD if the programmer is so inclined).
The 65816's BRL and PER instructions have been removed because all relative addresses are 24 bits now, +/- 8 megabytes of address space. This is selectable between 8 bit relative (+/- 127 bytes) and 24 bits with the new "SSR" and "SLR" opcodes (set short relative and set long relative). These set/reset another flag in the extended 24 bit PSR which controls relative address size. This allows instructions like BCS, BCC, BVS, BRA, etc. to branch a full +/- 8 megabytes if necessary, or the traditional +/- 127 bytes if conservation of memory is the goal.
JSL ($22) has been removed because all addresses are long anyway, and this operation has been re-used as "JRS", Jump Relative Subroutine, which uses the above mentioned scheme for describing a relative address.
That's enough for now, if anybody reading this is curious about this project I would like to invite comments and suggestions. I am trying to gauge interest in this project to see if it is something people want developed into a completed product, instead of remaining on my computer as just another one of my own personal software "toys"...
Steve Sviatko
ssviatko@gmail.com