Dr Jefyll wrote:
As long as you can produce
some sort of warmup activity I think you should be able to get the assumptions in step with reality before the actual, "real work" data transmission begins.
I've been thinking about this some more, and I now believe that every SPI response sequence should start with a 1=>0 transition, so that really simplifies things.
Dr Jefyll wrote:
After detecting a negative edge you'll re-program CA1 to detect a positive edge, and vice versa. But the performance hit might not be
too bad if you're willing to be a bit fanatical about how the thing is coded!
Here's my original code that uses D7:
Code:
FOR n, 0, 7
STX iora% \\ (4) Take clock (D1) low
ROL iora% \\ (6) Sample D7 (MISO) into C, and take clock (D1) high
ROL A \\ (2) C=1 after this, because A starts off as FF
NEXT
RTS
That works out at 12 cycles per bit.
Here's a completely untested version that uses CA1:
Code:
FOR n, 0, 7
// clock low, clear CA1 int, MISO changes on this edge
LDA #&FD // (2)
STA ora% // (4)
// Update active edge
LDA ifr% // (4) IFR bit 1 set if active edge seen
ROR A // (2) Move to bit 0
AND #&01 // (2) Mask off all other bits
EOR pcr% // (4) toggle active edge if necessary
STA pcr% // (4) bit 0 of A is now not(CA1)
// Accumulate value of not(CA1) in zero page sr%
ROR A // (2) C=not(CA1)
ROL sr% // (5) Accumulate result (bit 7 sent first)
// clock high, clear CA1 int
LDA #&FF // (2)
STA ora% // (4)
NEXT
LDA sr%
EOR #&FF // Invert to correct negation
RTS
This works out at 35 cycles per bit, so about 3x slower.
That's probably too much of a performance hit, but it would be interesting to see if this actually works.
Dave
Login
Register
FAQ
Search
