After much head scratching and CPLD code revision, I have hit a road block.

I am feeding a 14.318MHz TTL Osc into my 95108 CPLD and dividing it down to 7.159MHz to feed the PHI2 on 65816.

Using a 50Mhz Scope, the clock waveform looks terrible on both the TTL oscillator and the PHI2 output. I recall "Kc5tja" having issues with slow rise/fall times on the 65816 clock. I will try it on a 100MHz scope tomorrow.

I am going to slow the clock down (1 MHz) and see if the edges clean-up better. If they do, I might be able to place a 74ACxx buffer in-line to clean up the faster clock.

Some lower speed pulses from the 95108 come out with nice clean square waves so I know the 95108 can produce better edges.

I am using bypass capacitors on my test board, which is only 2.5x3.8 inches with 2 layers. My production board will have 2 layers plus a power and ground layer.

For those interested, I have placed the 95108 in between the 65816 and the RAM. I am using the PHI2 low time to access video data and the PHI2 high time to access RAM. My RAM has a 15ns access time and the PHI2 half-cycle time is 35ns. The 95108 is also latching the upper 8 address lines from the data bus and holds the CPU in reset while it copies a 32k EEPROM into RAM on startup (at PHI2/16 speed).

As you can see, I have a lot going on inside the 95108 and am using 90% of its resources.

I hope to get access to a logic analyser so I can see what's going on within each part of the circuit.

My video signal looks very good, so once I get the CPU talking to the RAM correctly, it should be ready.

Daryl

I think you'll be better served by a 74F-series device. I tried 74AC00 on my Kestrel-1 originally, and it still didn't like it that much.

OK. I'll give that a try if the 1MHz test works.
thanks!

Daryl

The 1MHz clock provided a very nice square wave on the PHI2 output. However, it still doesn't look like the CPU is executing the boot code.

My RAM is a surface mount part and I think I may have over-heated it trying to solder it down.

Lesson 1 of SMT soldering - use plenty of flux. I've been reading up on soldering SMT parts and flux is very important to a good connection.

Lession 2 of SMT soldering is use a temperature controlled soldering iron - the cheap pencil-type irons can easily damage your parts or traces.

I plan to modify the 95108 to perform a series of RAM read and write tests to verify proper (or faulty) RAM operation. If that fails, then I'll need to prep another board using lession 1 & 2 above.

I really don't think so. At a semiconductor manufacturer where I worked in 1984-85, I sometimes did infra-red thermal scanning of RF power transistors with a special microscope to find the temperatures of the hottest spots on a transistor die under load, typically at max rated output power but a specified bad SWR at worst phase. I actually saw transistors operating at 350°C, or 660°F. Of course it probably wouldn't last more than an hour at that temperature, but that was actually operating, not storage. I was told that the temperature where they "go pop" is about 500°C, or 930°F, from a thermal runaway situation where the thermal resistance increases rapidly as the temperature rises so they can't get rid of the heat anymore, meaning it immediately spirals out of control and the part destroys itself. If the heat is applied from the outside of the part (as opposed to generating the heat itself), I suppose the temperature can briefly be taken up higher than that without damaging the part. The thermal gradient would be very low that way.

To back up however, I must mention the reason I've read that the specified storage temperature limit on semiconductors in inexpensive plastic packages is rather low is because the plastic in contact with the chip itself-- the die-- can damage the die from some kind of chemical interaction. I don't know if passivation (kind of a glass coating on the die) would protect it from this, as I worked in applications engineering and did not pay much attention to the wafer fab process, and none of our transistors were encapsulated in plastic anyway.

I've been using the 950°F soldering irons for the last 30 years though, and have never damaged a semiconductor with soldering heat.

Well,

I'll find out after I run the RAM read/write tests. I may just have an open leg or solder bridge under the chip. Its an SOJ package, where the legs curl under the chip.

Thanks for the feedback.... I'd like to think I didn't burn it up.

Daryl

For a square wave to look even reasonable on a scope, the scope needs a bandwidth of at least 10 times the square waves frequency. On my 30MHz scope, a 14.318MHz signal looks vaugely sinusoidial! You need a 150MHz scope for a 14MHz square wave to look square.

The 65816 needs a nice, clean clock with very fast rise times. One way to achieve this is to use two fast buffers to buffer the clock signal. One buffer only drives the processor while the other drives the rest of the system. This stops bus loading from degrading the signal driving the processor.

Hope you find this useful

_________________
Shift to the left, shift to the right,
mask in, mask out,
BYTE! BYTE! BYTE!

Yes, I do. I was thinking my 50MHz scope was probably not fast enough. The 95108 did seem to work from the TTL Osc. without any complaints.

I am currently writing a memory test function into the 95108 to allow it to perform RAM read/write tests.

thanks for the advice!

Daryl

Excellent news to report. I started over on a new board with a better iron and more flux. The entire prototype is completed and it works!

The memory test function in my CPLD found an open data pin (fixed) and the 400MHz O'Scope at work found a few other CPLD logic errors (fixed). The clock pulses looked much better on the faster scope. Thanks again to smilingphoenix for that pointer. Clock rise and fall time is 4.5 - 5ns. Just under the wire kc5tja found with his Kestrel project.

I now have my test code running and its cycling through the colors with ease.

System clock is 14.318 MHz and the 65816 is running at half that - 7.159 MHz. I plan to add a second clock at 16 MHz so I can run the 65816 at 8 MHz.

The CPLD is running between very warm and hot - I am using every IO pin and over 90% of the function blocks and macrocells. I may try a heat sink to remove some heat.

Here is a brief breakdown of how it works:
CPLD is placed between CPU and RAM. It uses the low phase of PHI2 for video access, and the high phase of PHI2 for CPU access (like the Apple ]['s). System /RESET is applied to the CPLD, which holds the CPU /RES low while it copies the 32k EEPROM into $08000 - $0FFFF. It then releases the CPU /RES and it begins running. There is one register at $0240 that is used to select which bank is displayed. Default is $10000. With 512k, you have 7 banks to choose from. Page switch will automatically occur at the next Vertical retrace.

I now need to add the 6522's next. I kept the prototype board small to save money. Final version will be large enough to hold the 6522's.

Also want to play with the color palette and build some character and graphical drawing routines.

Will report more later. I plan to update my web site with more details too!

Daryl