Hi guys

Would someone be able to answer a quick question for me?
When writing to RAM from a 6502 you normally wait for the latter half of the PHI2 cycle to go high before allowing the /WE pin to go low on the RAM.
Is this due to the address not being reliable when pHI2 is low or possibly that data is written only on the rising edge of the RAM's /WE rather than any time /WE is kept high?

I ask as I've created a module designed to with an NMOS 6502A system and, after sending the gerbers off, spotted that I've not qualified /WE going low with PHI2 going high. I can modify the CPLD logic and put in a (bodge) wire from PHI2, but would just like to check if this will be necessary.

Cheers for any replies

You can sometimes get away without properly qualifying RAM write/reads and ROM reads, as I found out myself, but this is not the right approach as it will be very dependent on component selection, likely be unstable and will usually create problems you might not see (like bus contention) which could cause issue for you down the road (like when adding interfaces and such). Yeah, I was real good at making this mistake.

Take a look at the following threads, where I, and another, learned from the best folks on this site what to do and why. A lot is explained in these discussions including both what to do and what not to do.

http://forum.6502.org/viewtopic.php?f=4&t=5179
http://forum.6502.org/viewtopic.php?f=4&t=5180
http://forum.6502.org/viewtopic.php?f=4&t=5142

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Bill

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The practical upshot is that because the address isn't guaranteed to be stable until Phi2 goes high, /WE in particular needs to be Phi2-qualified. We usually qualify /OE as well because it's just as easy as merely inverting the R/W line, and it's also actually necessary for the '816 (which drives the data lines with the bank address during Phi1).

You will (especially with faster systems) get bus contention if you fail to qualify /OE. Found that out too. It never made any difference to how my badly configured machines ran (well, that I came across anyway), but it did make a difference on supply noise and current. Not a big difference on current, but more modern devices have pretty strong output circuits and it can't be good for them, or for controlling glitches on the power rials power rails, when you have a memory device trying to drive a data line low while the CPU is trying to drive it high.

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Bill

Thanks for the replies, guys.
I thought that it might be an issue. Been a while since I designed anything 6502 related and it just didn't occur to me until too late. Meh. But given that my adapter board sits in the CPU socket on the main board and the 6502A is then plugged into my board, I can easily take a bodge wire from the PHI2O pin and route it to one of the free I/O pins on my CPLD. I'm a bit annoyed at not thinking of this.
Anyhoo. Onwards and sideways, as they say!

If it makes it any easier, you could route from the clock source instead. This is in fact the preferred way for the WDC65C02, in case you want to upgrade later, and in my testing works well for all versions up to their rated speed (and usually a bit beyond). This is not specified, so some here might disagree.

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Bill

If it were a WDC 65C02S based system I'd definitely do this, but it looks like everything on the computer mainboard (not my adapter) is qualified with PHIO (pin 3) after being inverted. As such, I'll probably do the same and see how that goes. Just waiting for the PCBs to turn up now.

Have you considered using the extra active hi chip select input on a 64-KB (or larger) SRAM chip to qualify both read and write operations?

I've used the following NOS (New Old Stock) chips from Chinese vendors on AliExpress on my hobby projects over the last few years with good results;

The second select line is also present on 8Kx8 SRAMs, so in a truly minimal system it could be a reasonable way to save a gate. But EEPROMs seem to have that pin be a no-connect (thankfully not a don't-connect), and in most systems you'll need a ROM of *some* description. And it only takes three-quarters of a cheap 7400 to generate the signals *properly*.