For some years, it has been the case that what you order from eBay might not be what you actually receive. Frequently the advertisement is for a genuine WDC part, and the CPU will arrive with WDC markings from their earlier production runs (but with too late a date code), but actually turn out to be an NMOS part, or if you're lucky, an early CMOS part from Rockwell or CMD. Other times, a badly faded marking might be scarcely visible, yet alone readable, leaving you uncertain as to what exactly you have received.

There are fairly simple ways to distinguish an NMOS part from CMOS in software, provided you have a running machine. But if you've built your SBC anticipating a modern CMOS part, you'll probably find an NMOS CPU won't work at all - whether due to incompatibility of the glue logic and peripherals with TTL signals, or too low a supply voltage, or too high a clock speed. This inevitably leads to frustration.

What you need in that case is a test harness that will accept *any* genuine 6502 and identify it for you, using both software and hardware differences. As a bonus, since the most essential pins are the same, it should be possible to slot a 65816 (or 65802) into the same test harness and have that be identified, too. Only 6502 variants with incompatible pinouts, such as the 6510 or "mini" versions, could not be handled by a single board, unless extra sockets were fitted specifically for that purpose - but I think those are much less susceptible to counterfeiting, anyway.

The essential pins are RESB, A0-15, D0-7, Phi2-in, and R/W, all of which are identical in function across the whole family (except for bank address multiplexing with the '816). These are sufficient for attaching a small SRAM and EEPROM, a small LCD character display for output, and a 6522 VIA. The latter is to host cycle-accurate timers, produce IRQs, and probe some of the remaining control-side pins whose function varies between 6502 family members.

The W65C22N (not S!) and 74HCT family glue logic will work fine with both NMOS and CMOS CPUs, and a clock speed of between 100kHz and 1MHz ensures compatibility with even the slowest speed grades of NMOS. For ease of construction, a design using only through-hole parts would make sense. Hobbyists needing to test only a small number of CPUs might stick with a conventional DIP socket for the CPU, while some might prefer to install a ZIF socket to handle larger numbers quickly and without damage.

There is one wrinkle in the shape of the NMOS 6512, on which Phi1 is an input, not an output, and is required for correct operation. I think this could be handled safely by generating Phi1 externally, and feeding it to the relevant pin through a parallel RC connection and a jumper. On a 6502 the internal and external drives will be identical, so no significant current will flow. To identify the 6512, removing the jumper and thus the external clock will make it stop working, while a normal 6502 will keep going. This pin must also be tied low to run the 65816 correctly, since it becomes the ABORT signal. Hence the jumper should normally be left in the "no clock input" position, and only set to make a 6512 work; this jumper's state should be fed to a 6522 input for detection. NB: the 65SC12 (found in the BBC Master) does not require Phi1 input, and simply doesn't produce a Phi1 output.

There's also a (presumably rare) version that takes a crystal across two pins and divides the resulting frequency by 4, producing a quadrature clock signal on the Phi1 pin as well as a Phi2 output. This would leave the CPU operating at a quarter of the speed expected, and indeed out of step with the 6522. I think the 6522 might still be accessible in that condition, and 250kHz is still well within the range of acceptable NMOS frequencies, so it should be easy to notice this variant by observing instructions taking 4x as long as they should. It may also be feasible to rig up a detector to find where Phi2-out gets out of step with Phi2-in, and provide that detection at one of the 6522's inputs.

Other pins that can usefully be probed include:

• VPB (pin 1) which is marked Vss on both NMOS and early CMOS chips, and is apparently only VPB on WDC. The latter will read high except when actually taking an interrupt. A weak pull-down should ensure compatibility with early chips.
• RDY (pin 2) which is normally pulled high, but which executing WAI on a WDC part will pull low. The 6522's built-in shift register could be used to record a short-term history (every other Phi2 cycle), to be examined immediately after a WAI test (which will involve generating a timed interrupt).
• MLB (pin 5) which is NC on early parts, even some CMOS parts, and Vss on the 6512. It's present on variants intended for multiprocessing, and indicates when a RMW operation is in progress. It may be sufficient to attach this to the 6522's pulse counter input, with a weak pull-down.
• SYNC (pin 7) becomes VPA on the 65816, and thus stays high during a greater proportion of cycles (when fetching operands in the instruction stream, as well as opcodes). This is a sufficiently important way of distinguishing the 65802 from the 65816 to be worth installing a shift register to capture a cycle-accurate history, then accessed through one of the 6522's ports.
• Phi2-out (pin 39) becomes VDA on the 65816, and thus goes high during a smaller proportion of cycles (opcode fetches and data accesses only). This could be an additional method of distinguishing the 65802 from the 65816, but the sample point would have to be at mid-phase instead of at Phi2 leading edge, since the original use of this pin is unstable at the latter moment. This requires generating a quadrature clock, not just Phi1 and Phi2.
• SOB (pin 38) input on the 6502 becomes the multiplexed MX output on the '816. This should be pulled high, but its functionality can be checked by putting the '816 in native mode (having first established the possibility of doing so), and then setting both accumulator and index registers to 16-bit mode. This will pull the MX pin low on an '816, but have no external effect on an '802.

This might be a good excuse for me to get back up to speed with KiCAD…

It's a nice idea, but I really think the approach should be external, where you take some off the shelf micro controller to drive the conversation.

This way, you can make no assumptions about the chip under test (isn't there a 65xx variant out there that only has a 12bit bus?). The controller can clock the chip, can monitor it's lines, feed is instructions to run, etc.

The 65xx chips with limited address space (usually 4K or 8K) tend to rather obviously have fewer than 40 pins (that was the point!), so it's not necessary to test them to discover they're not a full 6502, and people are unlikely to accidentally get one as a counterfeit substitute for a 6502. The 6510 is an example of a pin-incompatible variant that's the correct size, though I haven't heard of anyone getting one of those by accident.

A *disadvantage* of using an external device to probe everything - which I did consider - is that you then have to program and wire up that device. While that's often not unreasonably difficult, it's still an extra set of tools that a new 6502 hobbyist might not have or subsequently need. Whereas they *are* likely to need a way to write an EEPROM, which is all this method needs. Or, if you go the Raspberry Pi route, you need to install level shifters to handle the NMOS parts safely, and most likely a multiplexer or three to reach all of the pins, *and* you need to achieve realtime performance guarantees to correctly drive the 6502 clock and sample the pins without dropping below the minimum cycle speed of an NMOS part. There are just too many complications; this way is easier in the end.

A disadvantage of *this* approach is that it's hard to probe for things like BE, which are absent on some of the older chips but are input only, and would disrupt operation of the CPU unpredictably if changed by software. I think it's reasonable to assume that BE goes with MLB; the signals listed above are almost certainly sufficient, along with software checks of opcode support and quirks, to identify every important variant likely to be found in the wild.

One advantage of something like this is that it's effectively a minimal SBC kit which is practically guaranteed to work if assembled correctly, even if you get a counterfeit CPU (as long as it's *some* kind of 6502), and even though it has very limited functionality. In short, potentially a big confidence booster for newbies. I could reasonably design in an expansion header, to allow it to be built up into a slightly more general-purpose device once it has served its original purpose.

Potentially chip resellers could use something like this as a filter, too, to protect themselves against unknowingly passing on a fake, or to resolve ambiguities when some random, faded chip is presented as "a 6502". These would be the guys wanting to fit a ZIF socket.

There is a small piece of code to detect the different variants of the 6502: NMOS, CMOS, Rockwell CMOS, 65802, early 6502 with bad ROR, Ricoh without decimal mode, Hudson HuC6280, Renesas 740 with/without MUL and DIV. In the case of NMOS you may be able to distinguish the different manufacturers by their illegal opcodes.
Look at: viewtopic.php?f=2&t=2263
Regards
Ralf

I'll review that in detail when I get around to the software side of it. Software tests can do a lot to identify the particular CPU core within the chip, but there are also hardware differences surrounding that core which can be relevant - not least the '802 vs '816 distinction. The '802 was an '816 core with a 65C02-like pinout.

Ok, your goal is to see the unknown cpu running safely in a socket. If you have this cpu running you know some details to distinguish some variants. At least you want to run this magic piece of software to answer the remaining questions. Right?


I know The Transwarp for my Apple IIe is populated with a 65802 since 1986 or 1987.

BTW how many 65802 are left today? I tried to get another one some months ago. But I did not find any wherever I looked for 65xx chips.

Ralf

But it's not the SBC they want, all this to test a $3 chip instead of buying a new one for $7 from WDC.

I know, I know, "vintage" and whatever. Either way it's a big investment.

Many of the components that go into the tester can potentially be reused in a custom SBC - one of the big advantages of through-hole components. The 6522, the SRAM and EEPROM, the 16x2 character display (itself a $10 kit from Adafruit), even the 74-series glue logic if sockets are cheap enough…

Sure, I don't quite understand the drive to buy 6502s from random Chinese eBay merchants, when brand-new WDC parts are available at frankly reasonable prices. Possibly some of it is that people don't know where to look for the genuine article, and just trust the search engine. Perhaps, too, they are scared of what the shipping and small-order charges might look like, if they order from a big catalogue like Mouser (who are one of WDC's official distributors). The fact is that newbies regularly show up on this forum with a mystery chip, sold to them as a genuine WDC part, but which most definitely isn't, and now they're having trouble with it.

This may work as a substitute for the 65802.

I bought all he stock I could find a while back.

_________________
Andrew Jacobs
6502 & PIC Stuff - http://www.obelisk.me.uk/
Cross-Platform 6502/65C02/65816 Macro Assembler - http://www.obelisk.me.uk/dev65/
Open Source Projects - https://github.com/andrew-jacobs

I've got some way into laying out the schematic for this. So far it looks very much like a standard (if basic) SBC, as most of the effort has gone into making the symbols representing the 6502, 6522, RAM and ROM chips - as well as learning my way around KiCAD as I go. It's not a very "discoverable" interface, and it has a lot of traps for the unwary.

(Apologies to BDD for not making this monochrome - I don't need advice on this, just giving a progress report of sorts. I plan to separate some of the auxiliary circuits with labelled signals, to help declutter the main part of the diagram.)



The 74HCT78 in the upper right corner is wired as a state machine to produce a quadrature clock from a 4x source. The latter is specified as a standard UART-frequency half-can CXO, but pretty much anything in the 1-4 MHz range should work. Having a quadrature clock means I can have the shift registers (not yet drawn) sampling both Phi1 and Phi2 phases at their midpoints - hence they won't be trying to sample signals which, in some cases, are specified to be unstable at the Phi2 clock edges (especially Phi1 and Phi2_O).

Since all of the support chips are CMOS rather than TTL, bus loading will be low, so even an NMOS CPU under test should be able to drive signals somewhat faster than specified - not to mention that typically a 1MHz part was simply one that failed a test at 4MHz, as in practice that was the criterion for the 2MHz speed grade. The truly paranoid might wish to use a maximum 2MHz oscillator, so that even a 1MHz NMOS or early-CMOS part is within official spec for midpoint sampling at 500kHz. The 1.8xx MHz oscillator that the 6551 takes will be fine for that.

Three-quarters of a 74HCT00 produce the qualified /OE and /WE signals, and a 74HCT138 decodes the top three address bits to provide chip-selects. There'll be one more output used from the '138 when I add the Adafruit display connector, and I may add a conditional qualification of the decode signal by Phi2_O to help deal with the corner case presented by the CMD 65SC102, which divides its clock input by 4 (and produces its own quadrature clock output on the Phi2_O and Phi1 pins). I think this extra circuit would sensibly use the remaining section of the '00.

Speaking of clock corner cases, a jumper arrangement to handle an optional 6512-required Phi1 clock signal is in - but presently this can't be detected by the machine itself. I'll need to rework that, and it'll most likely involve adding another 74xx chip.

I think I can get away with installing just two shift registers (one driven by each midpoint clock), plus a multiplexer chip to actually connect to all the signals of interest. I can then use one of the address lines to select which parallel output is presented to one of the 6522 ports (as the 6522 itself is only partially decoded and thus mirrors many times), leaving the other port free to drive the multiplexer and some other diagnostic controls (such as the Phi2_O qualification of chip select, which would otherwise cause trouble with the 6522 when used with a standard 6502).

More progress today, wiring up the shift registers and cleaning up the schematic layout somewhat. The quadrature clock signals (Phi3/4) are also now properly labelled.

Finished at last, at least in terms of the schematic.

I included a polyfuse to help guard against putting a completely non-6502 chip in - hopefully it'll heat up and go open before any chips do - and a bi-colour LED to indicate whether it is open.

I had to take an "interesting" tack for qualifying the /CE signals, to minimise the chip count. The reason /CE is qualified by Phi2_O at all is because there is one 6502 variant in which the Phi2 input is not directly usable as the system master clock, as it is internally divided by 4 and turned into a quadrature clock. This is not really a problem for reads, in this particular machine, but a single write will appear to be 4 consecutive writes - hopefully to the same address as each other. The VIA and RAM can probably cope with that, but the LCD module would probably object. OTOH, I can't unconditionally gate /CE, because that would violate the timing requirements of the VIA (/CE valid before Phi2 rises, but Phi2_O trails Phi2).

The system comes out of reset with the VIA ports at high-impedance input. So by default the Phi2_O pin will charge up the little capacitor through the Schottky diode, and thereby hold the '138's enable input high. This should be true even for the '816, where the Phi2_O becomes VDA, since the first valid accesses the CPU makes are data fetches (the reset vector), and every opcode fetch also drives VDA high. One of the first tasks of the Reset handler will be to configure Port B so that bits 0-4 and 7 are driven, not floating - as the W65C22N doesn't have bus-holding devices, unlike the W65C22S (which I can't use because TTL compatibility is needed to handle NMOS CPUs).

Subsequently, the VIA and shift registers will be reconfigured to sample the Phi2_O pin at the midpoints of the Phi1 and Phi2 phases, and a few instructions later it will be clear whether the Phi2_O pin is following the Phi2 clock faithfully or not. The VIA's cycle timers can then be used to determine (by executing an instruction sequence with known timing) whether the discrepancy is due to an '816-style VDA output or a divided clock. If the latter, the /CE gate can be turned on by actively driving PB5 low; this discharges the '138 enable whenever Phi2_O isn't actively driving it high. The need to do this is sufficient evidence to identify the '102 variants of the 6502 family, without examining the other pins' output, which is fortunate since the shift registers sample with the un-divided clock, not Phi2_O.

PB7 is wired to both PB6 and CA1, so that the Timer 1 pulse output can both be chained to Timer 2 for a long delay time (useful for the human-readable output phase of operations), and used to trigger a Port A input latching operation. The latter should allow more flexibility in sampling pin outputs during interesting instructions, rather than always having several cycles overwritten by signals associated with the VIA-reading instruction.

Now I get to explore the joys of PCB design, and incidentally write some software.

I'm interested in this. I'm covered with genuine WDC chips for now, but I will not buy any new ones - they're just $7 or so, but shipping is now three or four times that, so there won't be any new ones for me from Mouser or Jameco. Although I wouldn't buy "WDC" chips on Ebay, with maybe a single exception they're all fake. Rockwell chips, on the other hand, are interesting.

Note that that is not true of the W65C22N like it is of the W65C22S. The N version's inputs are like LSTTL loads.


Can you get away with a 74HCT245 bus transceiver, with the direction determined by R/W\?

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?