This is, what happens when software coded to work with a "40 characters per line display" uses an "80 characters per line display":



;---

Interlaced mode yes, but some conceptual problems in the circuitry:



;---

But enough for this week.
UARTs are next.

The article about building a simple TTL UART in the link of my previous post
is related to a PCB from that old TREX project.



But when trying to build an UART which supports different baud rates, parity,
variable word length and things like one and a half stop bits...
while trying to be "compatible" to an existing chip...
unfortunately is a much more complicated things to do.

For instance, consider to have three different clock domains in your design: CPU, RX, TX.
There are two different approaches to this:

1) you could try to synchronize the RX and the TX clock to the CPU clock.
Downside is, that this gives you a jitter in RX\TX which might be tolerable at low baud rates and a high CPU clock...
unfortunately, somebody might want to debug a CPU running at a low CPU clock frequency at a high baud rate.

2) you could try to synchronize Data and control signals between these three different clock domains,
what would bloat/complicate the circuitry a lot.

Unfortunately, I had voted for 2), and that's where the project had failed:
the more I had tinkered with the innards of the RX module, the less it worked.

Well, my TTL 6545 was sort of the "Klendathu edition": plenty of bugs at a considerable size.
For the TTL 6850\6551 project, bugs play in a different class of weigth... while being "nuclear powered".

Here we go:
X50, experimental TTL implementation of a 6850, FAILED (that's why I had reversed the colors of the picture)



For "6850", plugged into the 1X51 backplane, we have:
1* 1C50, control module
1* 2F50, flag and status module
1* 2R51, receiver module
1* 2T51, transmitter module
1* G50, baud rate generator module
1* D51, RS232 level converter module

;-------------------------------------------------------------------------------------

X51, experimental TTL implementation of a 6551, FAILED (that's why I had reversed the colors of the picture)



For "6551" plugged into the 1X51 backplane, we have:
1* 1C51, control module
1* 2F51, flag and status module
1* 2R51, receiver module
1* 2T51, transmitter module
1* G51, baud rate generator module
1* D51, RS232 level converter module

;==================================================================

What had failed, was the RX part (we later are getting to it), and the rest of the circuitry mainly was/is untested.

Noticed something ?
For economical reasons, the TTL 6850 and the TTL 6551 project both had used these modules:

1* 1X51 backplane
1* 2T51, transmitter module
1* 2R51, receiver module //FAILED
1* D51, RS232 level converter module

1X51 Backplane:

2T51 transmitter module:











If just looking at these schematics already gives you a headache... welcome to the club.

2R51, receiver module //FAILED



It stubbornly had refused to work.
And the more I had tinkered with its circuitry, the less it worked.
(The '2' at the start of 2R51 is the hardware revision. No digit means first revision.)

When trying to build a TTL RX module, PLEASE consider taking a different approach.
Also, that variable length RX shift register isn't a beauty, consider taking a look at the 74259 bit addressable latch, too.

D51, RS232 level converter module



//Configuration jumpers are "borrowed" from Daryl Rictor's SBC-2.
//Daryl, thanks for making the SBC-2 schematics available to the public.

Now we are through with the modules used in both projects: the TTL 6850 and the TTL 6551.

1C50, control module, TTL 6850 only:

2F50, flag and status module, TTL 6850 only:

G50 baud rate generator module, TTL 6850 only:

The 6850 chip comes without a baud rate generator... and for debugging I just had to add one.

We are through now with the TTL 6850, now for the TTL 6551 specific modules.

;---

G51 baud rate generator module, TTL 6551 only:



Edit: the 100nF capacitors are hidden below the IC sockets.

1C51, control module, TTL 6551 only:

2F51, flag and status module, TTL 6551 only:












...and with this, I think the complete set of schematics for my TTL 65XX peripheral experiments now went through.
Thank goodness!

But now I need a break.

Cheers.

Some failed prototypes (you recognize the pioneer by the arrows in his back):



The project for building these experimental TTL peripherals took me three years.
I already was sure this would be going to be my last hobby electronics project from the start,
so I had lighted the candle at both ends.

In November 2015, when I had noticed that Drass started building the C74 TTL CPU in the forum
by using the one or other thing from my homepage, I just had to drop the tools I had been holding in my hands,
stopped my project, then rushed to the forum for giving support for his project.

And I'm still confident that this was the right thing to do.

The schematics in this thread still are at least 3 years away from "production quality",
and don't be fooled: building your own set of TTL 65xx peripherals will take a lot of time and effort,
you better build your own designs from scratch...
...preferrably by not using a bi_directional internal data bus like I did,
because this complicates calculating the timing a lot when trying to aim for speed.

Oh, and all of my old hardware already went scrapped some time ago, sorry.
The Elektor Junior computer (my very first computer) I had donated to a friend in this forum.
Cheers.