6502 not asserting R/W for long enough

[mdpye]

GOT IT!

Cold solder joint on the CPU Vss pin. Gremlins were visible probing the chip pin directly, but not the rail immediately adjecent. It was additionally pre-confirmed when poking it with the scope probe ended up mechanically banishing the gremlins during the debugging session. Percussive maintenance is real.

Thank you everyone for your help. "Hello, world!" is go!

On the scope: for timing relationships (assuming gremlins are not visiting) I'm using a cheap USB logic analyser. It's running 16M samples / s, but my timings are plenty padded right now, so it is plenty resolution, because I'm not looking for fractional timing misses (yet).

I did use phi2 as an external trigger when looking just now and I was useful. I should buy a third probe so I can use both traces and the trigger at the same time.

On the 74 series chips, I'm using all HC series, so fast, but not too fast

Thanks again all!

[BigEd]

Hurrah!

[Dr Jefyll]

BigEd wrote:

Hurrah!

Yes, hurrah!

BigEd wrote:

That RnW waveform is very odd indeed.

It's hard to be 100% certain, but I think I have the explanation.

When Phi2 begins to rise, the CPU begins to drive write data onto the data bus. This involves pulling certain data lines low -- IOW, connecting them to the CPU's internal VSS. But instead of the intended effect, the result is for internal VSS to rise, because the VSS pin is not properly connected to outside-world VSS.

So, internal VSS rises... and this alters the CPU's perception of Phi2. Instead of being, say, 60% of the way from VSS up to VDD, Phi2 is now at about 30% or less -- IOW, low. And Phi2 low means the CPU will cease trying to drive write data onto the data bus.

This removes the reason for internal VSS getting pulled above outside-world VSS. Internal VSS returns to normal, and so does the CPU's perception of Phi2. The cycle repeats. An oscillator has been created.

( The photo shows R/W, and the center portion of that waveform is identical to what will be seen on internal VSS during the same time. The center portion shows the write cycle, and during write cycles R/W is connected to internal VSS. )

Moral of the story: don't fixate entirely on input and output pins. Their meaning hinges on what VSS and VDD are doing; therefore assumptions about the latter can trip you up. Faced with a baffling situation, don't assume VSS and VDD are as expected -- check.

-- Jeff

[mdpye]

Quote:

( The photo shows R/W, and the center portion of that waveform is identical to what will be seen on internal VSS during the same time. The center portion shows the write cycle, and during write cycles R/W is connected to internal VSS. )

I can confirm, the same waveform appeared on the poorly connected supply pin.

[BigEd]

Excellent sleuthing Jeff! I suppose it's a kind of extreme example of ground bounce, of inadequate decoupling.