I found what I did wrong...unfortunately I'm not sure if it can be fixed.

I used a NOR gate to tie RTC enable and EEPROM enable to WS2.

My reasoning was, if either goes low, the output will go high.

I don't think this is causing the WSG to lock up the way it is, but this is definitely a problem. The NOR gates need to be replaced with NAND gates, so if either goes low it will go high. The issue is, one of the gates on that chip is used (correctly) in the /OE output.

In fact, I'm not sure what's driving WS2 high, the only thing connected to it is the output from the NOR....strange.

Well, I have a nand gate laying around (bought a box of HC and a box of LS parts so I'd have them if I need them, and the HC one does have a 00 in it). I think I can selectively cut pins off each and stack them, and that might work. Before I do this though, I need to figure out what is driving WS2 high

Ok, I think I found the final issue with wait state generation. The /Q outputs of both latches for WS1 and WS2 are tied into a nor gate, so if either is high the output will go low, and by default, both are high, which brings RDY low. I don't know how I missed this, I must've read daryl's schematic wrong when assembling it. If I replace that with an OR gate, and replace the other gates with NAND gates, I think that will fix the problem with WSG. As far as the clock goes....I'm not sure what to do about it, I don't know where to begin to why it's outputting flat 0v.

EDIT: Actually, the /Q outputs need to be fed into an AND gate, so if either is low, the output is low, but if both are high, the output is high.

To test my theory I cut the pin from RTC to the NOR gate going to WS2, essentially turning it into an inverter for the EEPROM select. As expected, I'm now seeing oscillation on WS1 and WS2 outputs, but since they don't overlap low enough the RDY signal is staying low. Throwing an AND in place of the final NOR of the WSG should fix that, and I'll have working wait states (eventually I'll fix the RTC trigger, whenever I get to using the RTC).

Once I have this going, I expect it to boot correctly every time, rather than crashing sometimes (my main suspect is still slow EEPROM).

It feels like the traditional approach, of drawing out your logic design and then studying it, to simulate in your head (or in pencil) what's going to happen when, will be more efficient than switching out one gate for another. That is, I think if you slow down a bit, you'll move forward more quickly.

I took a break earlier specifically because of this, I was getting frustrated and I was making mistakes.

I reviewed the changes, and the logic is sound, my intial diagnosis of the errors was correct, although they might not be the *only* errors.

I think I misinterpretted the final stage of Daryl's design, and I made stupid mistake with the nors, I'm hoping not to find this anywhere else, but being new to this, it's probably a good bet that I will. I green wired an AND gate in place of the final NOR output, the WSG is no longer holding low all the time but it's not triggering now, and I'm presently diagnosing that. I've also pulled all chips except the CPU and EEPROM. If it goes on long enough like this I'm going to pull the eeprom and build a nop generator out of resistors.

At the very least, since I saved so much on these boards it wouldn't be horribly expensive to replace it with a board that is correct (and gets rid of the variable clock, I'll have to experiment with that chip separately before trying to include it in a full blown project). In a way I'm glad I'm running into these issues, the challenge is what's fun, and there'd be no challenge if it worked right off the bat.

One thing that worries me is, I'm not certain on my diagnosis of the eeprom being accessed too quickly. The data lines are toggling right now, indicating that there's data coming from the EEPROM (they're toggling reliably, my scope is able to hone in on a repeating wave form on each). I suppose it may be that the eeprom isn't quite getting the *right* data on the bus though, but we'll see. It also could've jumped somewhere random in EEPROM, and since the majority of it has been written to NOP, it would be easy for me to see the same waveform coming out of it constantly

Either way, I need to diagnose why WSG is not triggering now, because if I get that fixed, I think I may finally have this thing working.

So the reason that WSG is not triggering is the EEPROM enable is not triggering. The reason is my LOW16E signal, which is generated by comparing the top 8 address bits (A16-A23) to ground. It should be high when it's in the low 16 bits (which it should be) but instead it's outputting low with small spikes to about 0.5v at regular intervals. The top 8 address lines show these spikes too, but if anything this should mean it's outputting 5V with small spikes downward occasionally (I think this has something to do with the demux setup for the data bus that's causing the spikes on these lines). None of the address signal lines are getting high enough that they should trigger the 521's inputs. I don't think the chip is dead, but I am very curious as to what could've caused this

EDIT: I may've messed up my logic here, the 521 may work backwards to what I was thinking. It's a bit weird that it was...somehow reading EEPROM before though, or was reliably failing in a way that set XCE.

Yup, pulled pin 1 of the 521 (OE, so now it only outputs HIGH), and it boots right up, every time, disables the emulation light, even with power cycling. I'm about to verify bus functionality but I think this finally did it.

My poor board is a mess now though, with the green wiring and missing pins and pins pulled from sockets, technically if I want to use the low16E still I need to greenwire the output to an extra inverter I have on the board.

I think that even with all the time I spent reviewing the logic, I couldn't see these problems without experiencing them. But now I know, and version 2 will be even better!

Now, on to the actual point of this thread, programming this thing (after I put all the chips back on)

Hurrah!

Definitely, unfortunately until I green wire the 521 I can't use garth's memory expansion. But for most of the initial programs I want to run on this, I think it will be more than capable. The ultimate goal is a full stand alone machine, so I'll need to see about picking up a DIN-5 keyboard at some point, or build one (I picked up a cable end for DIN-5 on one of my orders should I choose to do so, but I'm not sure how those keyboards are read from).

Anyway, I've got a special surprise in the works for this thread, just reading the datasheet on VIAs right now so I can execute it. I might not get it done until later though, as I'm thinking about taking a victory break, to celebrate the success of getting the machine stable. It's a lot to take in, seeing a full computer designed and built by me actually operate.

So I got a bit busy the past few days but I think I've just finished the first rendition of my assembler, and I plan on testing it with some code I've been trying to (unsuccessfully) assemble. It seems all the assemblers out there supporing the '816 either don't like windows 10, or do not tell me what I'm doing wrong in a concise way, or just have no documentation on how to use them.

If this works, I plan on starting a thread for it, and I'll start listing out all the things it can do. It has met most of Garth's wishlist for new assemblers, although it does not include any advanced macro parsing yet (IF, UNTIL, REPEAT, etc). That is on the todo list. It does, however, support conditional assembly based on number of args supported, i.e.

This will only compile past IFMA if the number of vars provided is greater than the number provided.

Anyway, hopefully this works out, because I've been working on something that I didn't want to compile by hand, and the other compilers have let me down so far.

I just started my thread on my assembler, as I believe it's (about) ready, I realized I didn't do a lot of thorough checking of BCD precision used in compiling, so decimal numbers may cause issues, but I'm working on it presently. The thread is here

As promised. The surprise is here:



EDIT: sorry for rotation, and bad quality, my phone apparently didn't like my surprise