|
I originally wrote a 6502 emulation in a 70MIPs PIC processor (I am using a 90MIPS/100MIPs dual core for the 65xxT). I wanted to see how fast I could make it run. The code is in assembly and I was getting about a 14MHz 6502 emulation running at 64MIPs. With the 100 MIPs core, its now about 20MHz. I have been developing the 65xxT on a 1MHz 6502 system (1541 disk drive). That is 1us PHI0 cycle time, with at least 2 cycles required per instruction. I have complete control of PH1 and PH2 (generated like a normal 6502). When running code that is shadowed (or in the cache) there is no fetching from the actual bus required. Therefore I can execute about 8 instructions (average) within a single PHI0 cycle. I am tinkering with a way to automatically calculate the speed of the chips on the bus, like ROM and RAM. Things like a 6522 have to retain the normal PHI0/PHI1/PHI2 cycle time. But if the ROM and/or RAM is reliable at something like 220ns, then it is safe to say that you don't need to be waiting the normal PHI1 period to latch the data. I can simply accelerate PHI1 and PHI2 to be a faster cycles, using PHI0 as a reference when necessary to synchronize the bus. Internally (running from cache or shadow), the only synchronization necessary is when something outside of the shadow/cache is accessed. The code in the cache or shadow can go as fast as possible and it only slows down when needed for accessing something on the bus. The memory map of course has to be setup ahead of time to make this work. Basically, it's a variable speed 6502. The speed difference can be quite good. If you are in a loop doing a bunch of 6 cycle instructions like STA ($C0),Y and you can execute 8 of those within 1us, things can really fly.
|
Login
Register
FAQ
Search
