I'm designing a circuit in which I will have a 3.3v MPU connected to a 65C02 (in addition to the usual 5v goodies, such as RAM, EEPROM, GAL, etc). The MPU has diode protection on its inputs so all I need to prevent the 65C02 frying it is to put some 1K resistors in series in the assorted bus lines. However, according to the datasheet the minimum valid '1' voltage for a 65C02 is 0.7VDD, which would be 3.5V and so any 3.3v '1's coming out of the MPU would fall into the grey area between 1 and 0.

One thing I could do is to run the whole shebang on 3.3v, but from the datasheets I've seen so far most SRAMs and EEPROMs need 5v to run (although at least the ones I've looked at should work with 3.3v logic values)

I'd like to keep my design as simple as possible, so what do the crusty old timers here recommend? The 65C02 will be running at between 1 and 4MHz (still need to work out the max frequency)

1) The 65C02 / 65C816 datasheets are up to their old tricks again and the 3.3v signal from the MPU will work just fine, so use the resistors and don't worry about it
2) Choose SRAMs and EEPROMs that run off 3.3v and run the whole thing on 3.3v
3) Use two power rails, with the MPU and 65C02 running at 3.3v, the memory at 5V and all logic buses at 3.3v
4) Something else?

Resistors really kill the rise times and slow things waaaaaay down, so I'd stay way away from that. I'd do the whole thing at 3.3V. For some peripherals, you could do voltage translation, but don't plan on doing that for whole bidirectional buses. There's plenty of 3.3V SRAM available, but I haven't looked for 3.3V (E)EPROM.

It occurred to me that I could speed up prototyping this by putting the other MCU in an "8 bit baby" dev board and using a C64 as a surrogate for the 65C02 CPU. That way I can develop and test the code for the MCU without worrying too much about the 65xx part of the system, since the hard parts of that have been provided by CBM

Can I assume that, other than instruction set differences, a 1MHz 6510 can be used as an accurate facsimile of a 1MHz 65C02 for prototyping this? Any tips from experienced C64 hardware hackers?

I guess I also need to ask my 3.3v question again... and unfortunately I don't think I can run the C64 on 3.3v Garth, I see your point about the resistors and the implicit capacitance in the traces forming a filter that bends the pulse trains out of shape, but at < 4MHz is it really likely to cause problems?

The 6510 itself is simply an NMOS 6502 with a 5 bit I/O port located at addresses 0/1 (one for data, the other for direction, don't remember the order). Which means that the pinout is different.

The C64 itself is another beast. The address and data busses available at the expansion port is are shared between the CPU and the Video chip. So during Phi1, the Video chip reads the video memory, while during Phi2 the CPU does what it has to do. This creates problems for example with the 6522, that expects to have valid address lines at the beginning of Phi2 - where actually the video chip just has released the bus and the lines are unstable. To use a 6522, delay the rising edge of Phi2 with the dotclock for example (see for example http://www.6502.org/users/andre/cbmhw/c64csa/index.html )

The shared bus also needed an additional input on the 6510 IIRC, that allows to tri-state the busses so that the video chip can take over.



well, it depends - on the size of the resistor and the capacitance :-)
I rule out Open Collector signals at frequencies above 500kHz-1MHz. I have seen rise times for a /IRQ line on a long bus of as long as 3-4 cycles @1MHz, so I never assume those signals to be clock-related. For OC there even is a neat circuit I found somewhere with a FET that transfers in both directions :-)

But the resistor you describe still is for a totem-pole output (push/pull), so that is different. If the 3.3V is CMOS, my assumption is that a "high" on that 3.3V CMOS ouput is still in the valid range of a "high" on the TTL input side, so reading from a 3.3V is not the problem. Remember the different input/output levels of TTL and CMOS.

The other way round you need ICs that tolerate 5V input even when powered with 3.3V. Say, use a buffer of the 74LVC line.

I found this interesting thread elsewhere that discusses some of the logic level details:
http://www.embeddedrelated.com/usenet/e ... 0897-1.php

Hope this helps
André

Thanks Andre!

I'm going to be using the MPU as a simple slave device, behaving mostly like an SRAM as far as the C64 is concerned. I'll give it a E input that will take the PHI2 output from the cartridge port (when E is inactive the MPU pins will be programmed to all inputs), and an R/W signal plus address and data buses that will also be the ones exposed in the cartridge port. So I think that I can avoid the intricacies of the C64's DMA implementation.

OK, looking more at the assorted datasheets, it looks like I should be able to connect all the chips' buses to each other without need for level shifting, both using a C64 as a development environment and in the final version with a 3.3V 65C02. This is my reasoning, can anyone pick any holes in it?

According to the 65C02 datasheet (running at 3.3V),
VIH (D0..D7) = 2.3V..3.6V
VIL (D0..D7) = -0.3V..1.0V
VOH = 2.9V
VOL = 0.4V

According to the 65C816 datasheet (running at 3.3V),
VIH (D0..D7) = 2.64V..3.6V
VIL (D0..D7) = -0.3V..0.66V
VOH = 2.9V
VOL = 0.4V

According to the 6510 datasheet,
VIH (D0..D7) = 2.0V..5.0V
VIL (D0..D7) = 0.0V..0.8V
VOH = 2.4V
VOL = 0.4V

According to the MCU datasheet for its user pins,
VIH = 2.0V..3.3V
VIL = 0.0V..1.0V
VOH = 2.85V
VOL = 0.4V

Therefore, if I connect my C64's NMOS 6510 to the MCU via the C64's cartridge port, I'm fine because the MCU's data lines will output between 0.4V and 2.85V, which are both inside the 6510's "no fry zone" and also inside its VIH and VIL ranges respectively. The 6510 in turn will output between 0.4V and 2.4V, which fall inside the MCU's VIL and VIH ranges respectively. So not only will nothing get fried, but data will flow uncorrupted between both chips.

For the same reasons, I should be able to safely connect a 3.3V 65C02 to the MCU (a 3.3V 65C816 however has a much lower margin of error - is 0.21V over the bare minimum 2.64V for a '1' enough to call it safe? it's interesting that the voltage ranges are different for the '02 vs the '816, I wonder what that says about the differences between the two chips)

Is my math correct?

(incidentally, I found a really nice writeup on this topic at http://www.pericom.com/pdf/applications/AN066.pdf)

Sooo... the > 100 views and zero responses means that my math's OK?

The VOH of the 6510 is the minimum voltage you'll see with the load they specify. If the only load is CMOS which takes no DC current (except a few femptoamps of leakage), the voltage will no doubt be higher, but I'm not sure that it would be high enough to cause any problem. It might be good to experiment. That's the only thing I can think of offhand. I suspect WDC's 65c02 and '816 probably have the same I/O pin circuits, but that their documentation is a little messed up...again. With CMOS-only loads, they can pull up or down basically right to the rail, meaning almost 3.3V (3.29V?) with a 3.3V supply.