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 Post subject: Sync pin behaviour
PostPosted: Fri Mar 08, 2019 2:18 am 
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Simple question. Does SYNC go HIGH for only the first byte of an opcode fetch, or does it stay HIGH for as many cycles as there are bytes to fetch? For instance, the LDX #$FF is a two byte opcode, taking to cycles to fetch. Is SYNC high for both cycles?

Second question: Is this specific behavior different on an original NMOS part, as opposed to a modern 65C02?

Here's the context. I'm trying to set up an inverse assembler on my logic analyzer. I show SYNC being HIGH for as many cycles as an opcode has bytes. Meanwhile, the fellow on the EEVBlog forum that is helping me, has the same inverse assembler running on the same logic analyzer, and it seems to me that his SYNC must go low after the first byte of the fetch. He is running an original KIM though, which I presume has an original part. I'm am still mid conversation with the guy, so maybe all will be cleared up after his next post. Just though I'd query more minds while I wait!


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 Post subject: Re: Sync pin behaviour
PostPosted: Fri Mar 08, 2019 2:28 am 
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SYNC is high for the opcode byte only -- just one cycle. This is true for 6502 and 65C02. (On 65C815 that same cycle is marked by VPA and VDA both being high -- for '816, *that* is "SYNC.")

J. :)

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 Post subject: Re: Sync pin behaviour
PostPosted: Fri Mar 08, 2019 4:56 am 
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SYNC does not change during a WRITE operation either.

I just so happen to be knee deep in developing a 65xx emulator/accelerator board. If you use one of Saleae's LOGIC devices I can send you the .logicdata file of a 6502 starting up, coming out of reset, and then executing code (for a Commodore 1541 disk drive).


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 Post subject: Re: Sync pin behaviour
PostPosted: Fri Mar 08, 2019 7:39 am 
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Interesting projects!

As a reference, or just for fun, I recommend a good look at hoglet's project to decode 6502 behaviour, starting with minimal signals and reducing to surprisingly minimal signals:

The only time SYNC stays high for more than one cycle is if the fetch is extended by bringing RDY low: see this visual6502 simulation.


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 Post subject: Re: Sync pin behaviour
PostPosted: Fri Mar 08, 2019 12:14 pm 
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BigEd wrote:
The only time SYNC stays high for more than one cycle is if the fetch is extended by bringing RDY low
For the 65C02 another special case exists. The C02's undefined aka illegal opcodes include 32 which are one-cycle NOP's. Because the time to fetch one of these instructions equals the time to execute one of these instructions, coding a bunch of them in sequence will cause SYNC will go high and stay high for the duration of the sequence.

( Details on the C02's undefined opcodes are here. Although these are described as NOP's, there are various behaviors exhibited -- some of which generate bus activity which is interesting and even potentially useful. )

-- Jeff

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Last edited by Dr Jefyll on Fri Mar 08, 2019 1:46 pm, edited 2 times in total.

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 Post subject: Re: Sync pin behaviour
PostPosted: Fri Mar 08, 2019 1:21 pm 
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Dr Jefyll wrote:
For the 65C02 another special case exists. The C02's undefined aka illegal opcodes include 32 which are one-cycle NOP's. Because the time to fetch one of these instructions equals the time to execute one of these instructions, coding a bunch of them in sequence will cause SYNC will go high and stay high for the duration of the sequence.
Ha! So the 65C02 got an extra output pin! Probably useful for serial I/O. Together with /IRQ as input (used in the 6502-Badge) this could be a limited UART replacement. 8)
Most likely the code to achieve this will be pretty weird :mrgreen: .


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 Post subject: Re: Sync pin behaviour
PostPosted: Fri Mar 08, 2019 1:39 pm 
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Hee hee. Good point about the 'C02. We don't have a transistor-level model of that.

(Just had a thought: someone could hook up a 'C02 to a logic analyser and some signal generator, connect the GPIB control bus to the internet, and anyone could perform some cycle-by-cycle experiments remotely...)


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 Post subject: Re: Sync pin behaviour
PostPosted: Fri Mar 08, 2019 1:53 pm 
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GaBuZoMeu wrote:
Ha! So the 65C02 got an extra output pin! Probably useful for serial I/O. Together with /IRQ as input (used in the 6502-Badge) this could be a limited UART replacement. 8)
An extra output pin -- I love it! :lol: But don't you think it should be teamed up with the "extra input pin" -- /SO ? :P

BigEd wrote:
(Just had a thought: someone could hook up a 'C02 to a logic analyser and some signal generator, connect the GPIB control bus to the internet, and anyone could perform some cycle-by-cycle experiments remotely...)
This would be a terrific resource, if anyone cares to rise to the challenge. :!: And even better yet if we could also have an '816 available for cycle-by-cycle testing.

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 Post subject: Re: Sync pin behaviour
PostPosted: Sat Mar 09, 2019 8:01 am 
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Dr Jefyll wrote:
But don't you think it should be teamed up with the "extra input pin" -- /SO ? :P

You mean SOB (that's what it's called in the data sheet)? :D :shock: :wink:

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 Post subject: Re: Sync pin behaviour
PostPosted: Sat Mar 09, 2019 1:51 pm 
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The datasheets for Rockwell, CMD and NCR call it /SO. :wink:

GaBuZoMeu wrote:
Ha! So the 65C02 got an extra output pin! Probably useful for serial I/O.
Also the CPU's address lines are entirely eligible for a job like that.

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 Post subject: Re: Sync pin behaviour
PostPosted: Sat Mar 09, 2019 3:08 pm 
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Some datasheets use a B suffix to indicate an active-low signal. Most sane ones use an overline or a stroke prefix.


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 Post subject: Re: Sync pin behaviour
PostPosted: Sat Mar 09, 2019 7:15 pm 
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Chromatix wrote:
Some datasheets use a B suffix to indicate an active-low signal. Most sane ones use an overline or a stroke prefix.

Bill Mensch told me the "B" came from the fact that the equipment they used to write the first data sheets decades ago did not provide for the overbar possibility, so the "B" was used to stand for "bar."

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