65xx continuously variable clock

[Chromatix]

Not quite - don't forget to distinguish between RDY and /RDY. Also, you're currently generating ~(Phi2 | /RDY) twice, when you can reuse that signal, and you should try to minimise the gate depth from Phi2 to each control signal (use 3-input ORs if you can, or swap over the ~(Phi2 | /RDY) and /VALID_ADDR if you stay with 2-input ORs).

[BigDumbDinosaur]

Chromatix wrote:

One of the things we want to do with an '816, as opposed to a 6502, is to qualify /OE and /WE with (VDA | VPA), so as to suppress spurious accesses during "internal operation" CPU cycles.

Uh...no.

VDA and VPA would be used to qualify chip selects, not read/write logic.

[Chromatix]

In other words, to treat (VDA | VPA) as an extra address line?

[backspace119]

Something worth noting as we're discussing this, I don't believe triple input gates exist in the AHC family, that or I'm getting bit by mouser's filtering system again. I went looking because kicad doesn't have triple input OR gates for 74 series logic, but now I'm seeing that the AHC family doesn't even have triple input NOR or AND or NAND. I see one 8 input nand, but that's the only gate I've found with more than 2 inputs....this is a bit troubling, as I think I have a few triple and quad inputs throughout my design, I'll need to check those

BigDumbDinosaur wrote:

VDA and VPA would be used to qualify chip selects, not read/write logic.

This would definitely let us get a head start on getting the chips selected I believe, they're high before the rise of phi2 right?

[backspace119]

There are, however, some triple input gates in the LVC series, which up until now I thought was 3.3v only, but appears to accept 5v, and output 3.8v logic high at 5v operation. The unfortunate part here is it seems most of them are single gate chips (and small SMD packages). This isn't an absolute deal breaker for using them, but it does complicate things. The really nice thing is they seem to be very fast.

EDIT: probably the best solution is to use a CPLD for these things though, since the logic is pretty complex.

[Arlet]

For my 6502 using discrete gates I've also noticed that there's very little available in terms of >2 gate inputs, at least not with my constraints (3.3V, TSSOP and high speed). And even the few things that are available are barely faster than stringing a few gates together.

I usually get stuff from Digi-Key instead of mouser, and I'm quite happy with their search features. Even if you prefer ordering from mouser, you could still try the Digi-Key site for searching.

Another option is to check out manufacturer's web sites, although quality varies and you don't have everything in one place.

[Dr Jefyll]

Arlet wrote:

Even if you prefer ordering from mouser, you could still try the Digi-Key site for searching.

Digikey's search is *really* good, IMO -- a tool worth spending some time with. And yes there are 3-input gates out there.

BigDumbDinosaur wrote:

Chromatix wrote:

One of the things we want to do with an '816, as opposed to a 6502, is to qualify /OE and /WE with (VDA | VPA), so as to suppress spurious accesses during "internal operation" CPU cycles.

Uh...no.

VDA and VPA would be used to qualify chip selects, not read/write logic.

Other than a minuscule waste of power, I see no objection to qualifying read/write pulses instead of chip selects. But the scheme won't work with a VIA, for instance, which accepts Phi2 and CS, rather than /Rd and /Wr pulses.

( But a VIA can usually be trivially managed by tying the active-high CS directly to VDA.)

-- Jeff

[Arlet]

Dr Jefyll wrote:

Digikey's search is *really* good, IMO -- a tool worth spending some time with.

Excellent service too. One time I found a mistake, clicked the "report mistake" button, and got an e-mail less than 4 hours later explaining that they had fixed the problem.

[Chromatix]

Treating VDA and VPA as address signals rather than bus-control signals does make some sense, actually. You can generate ~(VDA | VPA) and drop it into the /OE pin of a '688, for example, instead of tying that pin low; some other comparators also have cascade inputs. I think the 74HC multiple-input gates are often fast enough to build address-decoding logic, since the addresses become valid early, so you can use those to help qualify addresses.

Then the bus-control signals are simplified to forms which don't require 3-input gates:

Bank_LE = ~(Phi2 | /RDY)
/OE = (~R/W | ~(Phi2 | /RDY))
/WE = (R/W | ~(Phi2 | /RDY))

[GARTHWILSON]

backspace119 wrote:

There are, however, some triple input gates in the LVC series, which up until now I thought was 3.3v only, but appears to accept 5v, and output 3.8v logic high at 5v operation.

That's at a whopping 32mA output current. At 100µA output current, it can reach Vcc-0.1V or better, according to the data sheet.

[BigDumbDinosaur]

Chromatix wrote:

In other words, to treat (VDA | VPA) as an extra address line?

Not exactly. The two signals tell you when the '816 is generating any valid address.

In my POC units, I used VDA || VPA = 1 to qualify chip selects for anything in the I/O range, as that is where problems are like to erupt when the '816 puts indeterminate content on A0-A15. /RD (/OE) and /WD (/WE) are qualified by Ø2.

Incidentally, VDA && VPA = 1 with the '816 is the equivalent of SYNC = 1 with the 65C02.

[Chromatix]

Well, I know that much. VDA and VPA are not *literally* extra address lines, though they can be used to divide data and program address spaces (which is probably more useful in context of an MMU). I was merely suggesting to incorporate them into the address-decoding circuitry so that the /CE lines are effectively qualified by them; effectively creating two address spaces, one of which has no devices at all mapped to it.

If you use it specifically for I/O space, then you only really need to use VDA, since you're unlikely to execute any code directly from an I/O device. But here we're likely to want to qualify ROM space, specifically to avoid unnecessary wait-states being triggered (I think a lot of internal-operation cycles end up putting $xxFFFF on the bus, which might often map to ROM).

[backspace119]

Chromatix wrote:

Well, I know that much. VDA and VPA are not *literally* extra address lines, though they can be used to divide data and program address spaces (which is probably more useful in context of an MMU). I was merely suggesting to incorporate them into the address-decoding circuitry so that the /CE lines are effectively qualified by them; effectively creating two address spaces, one of which has no devices at all mapped to it.

If you use it specifically for I/O space, then you only really need to use VDA, since you're unlikely to execute any code directly from an I/O device. But here we're likely to want to qualify ROM space, specifically to avoid unnecessary wait-states being triggered (I think a lot of internal-operation cycles end up putting $xxFFFF on the bus, which might often map to ROM).

I didn't know this, and knowing it now it may be very important to do this to avoid accidental wait states.

GARTHWILSON wrote:

backspace119 wrote:

There are, however, some triple input gates in the LVC series, which up until now I thought was 3.3v only, but appears to accept 5v, and output 3.8v logic high at 5v operation.

That's at a whopping 32mA output current. At 100µA output current, it can reach Vcc-0.1V or better, according to the data sheet.

Wow, ok, so then the LVC series is probably something to look into then, although a lot of what I was seeing was single gates.

Chromatix wrote:

Treating VDA and VPA as address signals rather than bus-control signals does make some sense, actually. You can generate ~(VDA | VPA) and drop it into the /OE pin of a '688, for example, instead of tying that pin low; some other comparators also have cascade inputs. I think the 74HC multiple-input gates are often fast enough to build address-decoding logic, since the addresses become valid early, so you can use those to help qualify addresses.

Then the bus-control signals are simplified to forms which don't require 3-input gates:

Bank_LE = ~(Phi2 | /RDY)
/OE = (~R/W | ~(Phi2 | /RDY))
/WE = (R/W | ~(Phi2 | /RDY))

Ok, I may need to simplify other parts of my design down to use 2 input gates. The VDA and VPA as extra address lines is a neat idea too.

[GARTHWILSON]

backspace119 wrote:

Wow, ok, so then the LVC series is probably something to look into then, although a lot of what I was seeing was single gates.

That's 74LVC1G__. There's also VC2G and LVC3G, although probably with fewer options. (I didn't compare in detail.) Sometimes 1G should be easier to route, rather than having to take traces farther in order to use another section in an IC that's some distance away from where you need it.

[backspace119]

So here's my /OE /WE circuit now, as far as VDA and VPA go, I've got VDA qualifying all accesses to any IO, and VDA | VPA qualifying access to the top 8 bits (2 4M memory modules).

I've attached /OE and /WE to the /OE and /WE of all devices that use wait states, the RTC, EEPROM, and DUART (28L92). Other devices are still qualified off my READ, WRITE, and /READ, /WRITE signals, which are made by R/W and PHI2

If this checks out I'm going to look at the clock circuit, and see about either changing it back to a oscillator can or possibly leaving it, but not using it for slowing the clock to talk to devices. One last thing here, iirc using this circuit I've attached I don't need to worry about absorbing clock pulses, since the /OE and /WE of devices won't be pulsing off the clock now, is this correct?