drogon wrote:
I have a GAL 22v10 on mine. Saved me mucking about with a small raft of TTL.
I did start with the whole "retro" idea when I made my little SBC - wanted a classic memory mapped video system, old style UARTs, and whatnot, however as I started researching chip availability I sort of decided that to go down that route may be somewhat challenging - especially when I had initially set 8Mhz as my target speed, so I figured 1982 might be a good date - (When the BBC Micro came out) at that point we had ULAs and early PALs - the ATmega is my ULA - actually more as it now incorporates a disk controller, and the GAL is just a PAL to save me 3 or 4 TTL chips on the decoding and interfacing side of things.
So hat's off for trying to stay very old-school!
-Gordon
Thanks, although the audio/video generation that are planned are currently very *not* old school, due to chip availability. I don't think many VICs exist anymore like you find on the C64, so I'm planning to opt with the VLSI chip, the vs23s010, which is addressable over SPI and creates composite signals off its internal sram. Someone recommended it to me in my other thread, may've even been you, I can't remember now. For audio, I'm going with another VLSI chip, the VS1000, which plays ogg files. I'll have to figure out getting ogg files on and off the thing (since I don't have a file system planned currently) but other than that it seems pretty turn-key. For actual audio syntesis I have a daugher board planned that will do midi in and out, and also be able to synthesize some basic wave forms (maybe complex ones too, we shall see).
Speaking of daughter boards, I had an idea for another one earlier, and, I'll either start a new thread or put this in my old one probably, since it doesn't really belong in this thread, but being a cool idea, I just have to write it down here.
I've been considering creating a daughter board to handle some "ISA" extensions that exist in x86. Basically, it would be a massive ALU built out of logic chips. The idea is to use multiple 8 bit latches to form the entire width of it (for 256 and 512 bit math), and an 8 bit latch for the instruction to run. If I wire it right, it could be set up in such a way that the arithmetic logic would always be on, meaning you feed it an instruction, and then feed it data, byte by byte, and by the time you're done, it already has the answer, since the prop delays start as soon as it has data in the latches.
I think it's the coolest thing I've thought of yet, and maybe someone else has already thought of it and done it, but it seems like an easy way to allow the 65xx, with its modest 8 bit bus, handle large width machine words like 256 and 512 bit instructions do on modern x86 CPUs.