Well, the '245 is actually just the bus transceiver, which you don't really need anyway. It's the 8-bit transparent latch - the '373 - that you need to worry about in this context.

You need the '373 to be open for writing only when Phi2 is low and RDY is high - a slightly awkward combination to implement, as you'll need to invert one of the signals on its way into a suitable gate. The LE input is active-high, so you want ~(Phi2 | ~RDY) for minimum propagation time from Phi2. This will replace the inverter you presently have between Phi2 and LE, so there should be very little overall effect on propagation time (a NOR gate and a simple inverter both count as 1 gate in CMOS).

From this I gather you expect that RDY being low won't stop a Bank address from appearing as usual when Phi2 is low, is that right? Not arguing, just curious whether a source can be cited. As far as I know WDC doc fails to declare one way or the other regarding this point. I recall someone opining years ago that RDY low *would* stop the Bank address from appearing when Phi2 is low, but again I don't recall a source being cited.

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

The WDC datasheet is spectacularly unclear on this point. The precise wording is:
These two statements, appearing next to each other in the original datasheet, are directly contradictory. If "the Data Bus is held in the data transfer state" as if Phi2 were held high internally, then latching the bank address when the external Phi2 goes low during a RDY-low wait-state (as instructed by the second sentence) is likely to corrupt the bank address during the second half of the (slowed) memory cycle. And unlike the 65C02, there is no Phi2 output from the '816 to use as a reference to the internal state of the clock.

So gating the '373 with RDY as well as ~Phi2 is the safe option. It'll work correctly whichever of the two statements made by WDC is actually correct, and should have no effect on the speed of the logic.

Agreed, the extra gate does no harm, although it strikes me its precautionary nature might've been worth mentioning.

In any case, thanks for supplying the supremely contradictory quotation! Using one of the phrases, I was able to search the forum and find the previous discussion. In 2015, forum member cr1901 settled the matter with a hardware test of a real '816, and reported, "The 65816 does NOT drive the bank address while RDY is low." [Edit: oops, this means the extra gate *is* required, contrary to what I was thinking ]

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Which means the extra gating *is* necessary. (I think I remembered that discussion, but couldn't immediately find it.)

By the time external Phi2 goes low for the second half of the cycle, the data bus has either been driven by the CPU, or is tri-stated, or has even started to be driven (unstably) by the target device. The probability of the latter becomes quite high by the time the rising edge of Phi2 comes along. It's not possible to assume that the bus has kept the ghost of the bank address around for that long.

WDC *have* occasionally been known to correct some of their more egregious datasheet errors when intelligently pointed out… hint hint?

My mistake; had the thing upside down in my mind. Glad we got that prior reference sorted out, though.

You lurked the forum for three years before joining? Interesting.

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I may have gone through older threads at some point.

Thinking about it, I suspect that same thread was linked to in other, later discussions of the '816 which I read directly.

I really gotta start actually looking at the page numbers at the bottom before looking for new posts. Anyway, now that I know there are tons of replies to this:

I was on a long adventure through this old topic again, now understanding most of the comments here and actually reading them rather than skimming them like the first 2 times I went through it. I had deduced from this that it would indeed be the 573 that needed qualifying, since that is the part that happens in phi2 low, and the '816 is held in the phi2 high state when RDY is low. Also, the 245 isn't even a latch (silly me). It seems you're referring to the very thread I was going through Dr. Jefyll, and, although it doesn't mention wait states, it should most certainly be part of any newbies journey to implementing an 816. After all this is said and done, I may try and compile some of the resources I've used for making this, and add a supplementary to Garth's primer, from the newbies point of view.

So, with this figured out, it should be pretty straight forward to do the wait states, all I need is RDY high qualified with PHI2 low on the 573.

A side note, I saw ABT and FCT devices mentioned in that thread, I looked them up, they look really fast and cheap (at least the ABT ones do). I see the technology is BiCMOS...I don't suppose this will cause any problems, or that a newer tech has been released that's even faster (maybe this question should go in my newbie thread)

Another question, since RDY is bidirectional, I should not tie anything directly to RDY, but instead insert a 3.3K resistor between RDY and any input, correct? I already have the resistor, tied to 5v, just making sure I'm still going to be driving this correctly.

Yet another question: in Daryl's wsg he has OE only enabled if WS1 or WS2 are asserted, is this necessary? I can implement this with a NAND over top of an OR with a leg tied to the original OR input, but if I don't need it I can use a single NOR gate instead, without the OE qualification.

The RxC time constant might be a problem with a fast clock. You might need a 20pF or 47pF capacitor across in-line signal resistors (but not pull-up resistors) to remedy that. Post your idea before committing.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Alright, here's my WSG:



and here's my RDY line: (with the added cap you just suggested)



EDIT: that RDY line goes directly into RDY on the '816 after the cap+resistor, sorry for omitting

so if the capacitor goes from pin 10 of the NOR to the RDY input of the processor, that looks good. (We'll see if I still think so after I've gotten some sleep. I've staying up half the night to get the tax stuff ready for the appointment with the accountant in the morning. zzz...)

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Haha, I do some of my best work in the middle of the night, so I tend to be on at very unusual hours, at this point, I've got a meeting for work at 10am (I work from home, no tired driving here) so I'll probably be up the rest of the night.

Are you aware that in WDC parts, the RDY signal is bi-directional?

If you execute the WAI instruction on a WDC 65C02/65C816 then it will drive the RDY line low.

Hopefully you'll never deliberately use that instruction, but a code crash, jump to the wrong location and who knows what may be executed... (I use it both ways on my Ruby 6502 board)

-Gordon

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--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/