All good points, Ed. If we intend to operate beyond the manufacturer's rated specs then the burden of testing falls on us.
backspace119 wrote:
EDIT: I've been told wait states must be locked to clock rate. so this won't work, but I can still wait state off the variable clock
Wait states off the variable clock -- yes, I think that's your best bet. And RDY would be used to generate the wait states.
I realize this falls somewhat short of your apparent goal, which seemingly is to
fully optimize the speed of
both EEPROM and non-EEPROM bus cycles. However, the tradeoff is a favorable one. You end up with a nice, simple circuit, and the non-EEPROM bus cycles *are* fully optimized. EEPROM bus cycles get
somewhat optimized, with the sole restriction that the amount of extra time must be an integer multiple of one entire cycle. That may be no restriction at all, if the numbers happen to work out exactly. In the worst case you'll have almost one entire cycle of unnecessary delay, which is not the end of the world when you consider that EEPROM accesses are an occasional thing -- they don't necessarily dominate the overall performance of the computer, given that EEPROM accesses may be considerably outnumbered by non-EEPROM accesses (such as zero-page, stack, I/O etc).
It
is possible to reach your goal of optimizing the speed of both EEPROM and non-EEPROM cycles, but the performance boost compared to Plan A is likely to be small to none. Moreover, RDY can't achieve this, and the alternative (ie, clock stretching) demands logic that's considerably more complex than that required by RDY.
( RDY is generally used with a constant frequency applied to the CPU clock input... and when RDY is false, it tells the CPU to repeat the current bus cycle in its entirety. With clock stretching, RDY is tied high (ie, unused), and
the signal applied to the CPU clock input is variable. But fully realizing your goals would require generating *two* independently and continuously variable clock pulses, and selecting between them on the fly. You'd have to ask yourself whether you're equal to the challenge, and whether the questionable advantage is worth the extra effort and the risk to your project's success. )
-- Jeff
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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