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Also, I'm. Not clear what the advantage is to tying RW to PH2. As I have it now, RW is asserted for both halves of PH2, but CE is only asserted when it's HIGH. Aren't the data lines still tri-stated (or however it happens) when CE it's not asserted, regardless of RW?
You need to zoom in on the handful of nanoseconds around the falling edge of Phi2 to understand this part; the precise order in which things occur really does matter here. I tried to explain this earlier, but let's try again.
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Looking at your oscilloscope trace, it's clear that Phi2 falls, *then* R/W goes high, *then* /CE goes high. According to WDC's datasheet, R/W is guaranteed to remain stable after Phi2 for the same amount of time as the address lines are guaranteed to remain stable - which is *not* to say that both are guaranteed to change simultaneously. But we *can* infer that /CE is not going high (and deselecting the device) until a time at which the address lines are no longer stable, and may in fact have been detected to change by the device. Furthermore, your device might be expecting a "data hold time" in which the data bus remains stable *after* its control signals are driven inactive.
Much of this is because you're implementing your Phi2 qualification of /CE through a rather complex and relatively slow logic device, the '688. You should assume that most such devices, especially in 74HC series, are several times slower than a simple gate. Refer to the datasheets for details.
In many RAM and especially ROM devices, the response to /CE and address lines is also somewhat slower than to /OE and /WE. This does not mean that the device is *guaranteed* to respond slowly to address line changes; it *does* mean that you must satisfy a longer setup time in order to guarantee *correct* operation. This will exacerbate the effects of the relatively slow logic in the address-decoding chain. The end result is a potential write to a different address than intended, as well as to the intended address. This is sufficient to explain your corruption problems.
By explicitly qualifying /WE and /OE with Phi2 with just a single gate delay, we can make all memory devices insensitive to changes in the address lines and R/W from the CPU, before the CPU actually changes them. That's how the 65xx bus was designed to work, and essentially all devices are designed to work with that sequence.
Now consider the following hypothetical: your UART responds to /WE going high more quickly than your VRAM does, and starts driving the data bus with the contents of some internal register while the VRAM is still sensitive to data. That would allow the UART to corrupt the VRAM when the latter is written.
Meanwhile, reading back from VRAM will sometimes cause both the VRAM and the UART to drive the data bus simultaneously, resulting in temporary short-circuits. That is *not* specific to your timing problems, only the faulty address decode.