65XX SBC general help and color display help needed

[GaBuZoMeu]

drogon wrote:

They're designed as a drop-in replacement for the 7805, so it's highly unlikely you'll notice anything. I've used them in various projects over the past few years and they "just work", however I've never tried to measure any noise from them - mostly because they just work... I suspect you'll see more noise, etc. from the rest of the circuit though.

-Gordon

So far at least one sort of them (no manufactorer name as I am unsure) require a little load to run stable. In our case we have had ca. 2.5 mA quiescent current which causes the regulator to pump. Adding a "voltage prresent" light by using a very poor efficient LED (ca. +10mA) helps.

[GARTHWILSON]

I use SMPSs for our audio circuits at work and I get them really quiet; but I add extra LC filtering to do it, at both the input and output. Also, SMPSs are not well behaved over a wide range of load currents like linear supplies are. The inductor size should be chosen for the expected load range.

[backspace119]

So, I may've painted myself into a corner on routing. The density of chips is making it pretty hard to get all the traces through, here's a picture of the current routing (although I know it's hard to tell what's going on)

Any tips on routing that may make this easier? I may have to rip some or all of this up

[GaBuZoMeu]

You have placed some ICs tighly together (U2 <=> U29 or U5 <=> U7). Sometimes the bodies are larger and require a space between them. You can simply use a perfboard to check this.

[backspace119]

GaBuZoMeu wrote:

You have placed some ICs tighly together (U2 <=> U29 or U5 <=> U7). Sometimes the bodies are larger and require a space between them. You can simply use a perfboard to check this.

The gray corutyard for each should be the size of the corresponding socket for them, since I have socket footprints on every chip. I may end up spreading them out some, not only to combat the possible fitment issue but also so I can actually route everything correctly

[Dr Jefyll]

backspace119 wrote:

Any tips on routing that may make this easier?

If it's a "blank sheet of paper" situation, I begin with the widest buses and concentrate on keeping them short by playing with the prospective positions of the chips. Usually this means the CPU and memory will be adjacent to one another (because the address bus is the widest bus... and usually most of it connects only to the CPU and memory).

Next is the data bus, which is narrower but extends to a larger number of IC's. Still, you wanna maintain focus on the CPU and memory, with a view to optimizing both the address and data buses. Take some time to spin the chips around (I mean change their orientation) and find all the different ways they can abut one another.

You'll know when you've found a good layout for CPU and memory, because most of the connections between the two will be mutually parallel -- not at right angles, or zig-zagging this way and that to reach their destinations.

Having sorted the buses -- and you may discover two or three nice, tight arrangements from which to choose -- you're in a good position to plan the more highly random circuitry which remains.

-- Jeff

[backspace119]

Dr Jefyll wrote:

backspace119 wrote:

Any tips on routing that may make this easier?

If it's a "blank sheet of paper" situation, I begin with the widest buses and concentrate on keeping them short by playing with the prospective positions of the chips. Usually this means the CPU and memory will be adjacent to one another (because the address bus is the widest bus... and usually most of it connects only to the CPU and memory).

Next is the data bus, which is narrower but extends to a larger number of IC's. Still, you wanna maintain focus on the CPU and memory, with a view to optimizing both the address and data buses. Take some time to spin the chips around (I mean change their orientation) and find all the different ways they can abut one another.

You'll know when you've found a good layout for CPU and memory, because most of the connections between the two will be mutually parallel -- not at right angles, or zig-zagging this way and that to reach their destinations.

Having sorted the buses -- and you may discover two or three nice, tight arrangements from which to choose -- you're in a good position to plan the more highly random circuitry which remains.

-- Jeff

This is a better idea than how I started, which was with the 5V power distribution (fat lines, figured I'd do them first). I may rip up everything and re-arrange the board again, because the busses are going everywhere right now (the 6522 is a real pain because of all the PA and PB pins).

Ultimately, I think the address and data busses are going to have offshoots (for DUART and 65SPI at least, and possibly some other chips) is this ok?

[Dr Jefyll]

backspace119 wrote:

Ultimately, I think the address and data busses are going to have offshoots (for DUART and 65SPI at least, and possibly some other chips) is this ok?

Sure. They need to attach to the "core" (memory and CPU) somehow. All I'm saying is, figure out the densest part first. After that, you'll probably have some freedom to improvise as you lay out the rest.

Things are a lot tougher if restrictions exist before you start. An example might be if you have a card-edge connector that can *only* go in one certain location on the board (ie, the edge) -- and all the address lines have to connect to it. But you don't seem to be faced with that.

What's easy is stuff like the connectors you have attaching to Port A and Port B of the 6522's. There's no reason (as far as I know) that those connectors need to go in any particular location on the board. That means you have complete freedom to put the 6522's in whatever place makes sense, relative to the core. Having chosen a good spot for the 6522's relative to the core, you can then place the connectors in the same area where the 6522's are.

The same is true of almost any connector. The connector probably attaches to a cable anyway, and usually there's no problem with making the cable a little longer -- and that gives you the freedom to locate the connector wherever the heck you please!

[backspace119]

Dr Jefyll wrote:

backspace119 wrote:

Ultimately, I think the address and data busses are going to have offshoots (for DUART and 65SPI at least, and possibly some other chips) is this ok?

Sure. They need to attach to the "core" (memory and CPU) somehow. All I'm saying is, figure out the hardest part first. After that, you'll probably have some freedom to improvise as you lay out the rest.

Things are a lot tougher if restrictions exist before you start. An example might be if you have a card-edge connector that can *only* go in one certain location on the board (ie, the edge) -- and all the address lines have to connect to it. But you don't seem to be faced with that.

What's easy is stuff like the connectors you have attaching to Port A and Port B of the 6522's. There's no reason (as far as I know) that those connectors need to go in any particular location on the board. That means you have complete freedom to put the 6522's in whatever place makes sense, relative to the core. Having chosen a good spot for the 6522's relative to the core, then place the connectors in the same area where the 6522's are.

The same is true of almost any connector. The connector probably attaches to a cable anyway, and usually there's no problem with making the cable a little longer -- and that gives you freedom to locate the connector wherever the heck you please!

The one issue is the 6522s also connect to some other things (text display, video card port, audio card port, DIN-5 connector, vertical card edge (cartridge) connector), I suppose locating these all in a fairly close space will help, rather than having them on literally opposite sides of the board like I have now

I think I'm going to switch to a 4 layer board here, to minimize performance issues and allow power and ground routing to be already done. The problem is, OSHPark 4 layer boards are horrendously expensive ($10 per square inch, which at 45ish square inches right now, brings it to $450. You do get 3 boards with the order, but still). I've found some chinese suppliers but they're closed till the 11th for chinese new year, any suggestions on good board manufacturers? (I've decided I'll make a much simpler design after this that I can actually make on my CNC, this one will not be possible)

[Dr Jefyll]

backspace119 wrote:

The one issue is the 6522s also connect to some other things (text display, video card port, audio card port, DIN-5 connector, vertical card edge (cartridge) connector), I suppose locating these all in a fairly close space will help, rather than having them on literally opposite sides of the board like I have now

"All along one edge" might be fairly easy to arrange. Is that as good as "in a fairly close space"? It's your call.

As for four-layer boards, I guess no-one ever regretting going that route, and it does shrink the layout somewhat. But in regard to the whole AC performance / signal integrity ball of wax, I believe a person can succeed with only 2-layer as long as common sense is exercised and the goals aren't bleeding-edge.

The main rule is to arrange that every signal path (ie, address line, decode signal, whatever) has a return path nearby which takes roughly the same route, with no lengthy detours. This implies more or less a grid of ground connections -- and ideally you want the ground pin of every IC to locate at an X-Y intersection of the grid. In practice the grid may be irregular and incomplete, but that's alright -- and, if not, you can always augment the grid later by soldering in some point-to-point ground wires after the fact. It's kinda-sorta like having a 3rd (or even 4th and 5th) layer. That's my $.02 worth, anyway.

BTW, CNC-milling circuit boards is an idea I played with back in the 20th century. I'm tempted to drag out one of the old specimens so I can take some photos to share!

- Jeff

[DerTrueForce]

The way this is sounding, you're building something like a PCs motherboard, but 65xx-based. It might be worth designing on similar lines, at least in terms of layout. All the IO ports in one area, and the expansion slots lined up next to one another.

[backspace119]

Dr Jefyll wrote:

backspace119 wrote:

The one issue is the 6522s also connect to some other things (text display, video card port, audio card port, DIN-5 connector, vertical card edge (cartridge) connector), I suppose locating these all in a fairly close space will help, rather than having them on literally opposite sides of the board like I have now

"All along one edge" might be fairly easy to arrange. Is that as good as "in a fairly close space"? It's your call.

As for four-layer boards, I guess no-one ever regretting going that route, and it does shrink the layout somewhat. But in regard to the whole AC performance / signal integrity ball of wax, I believe a person can succeed with only 2-layer as long as common sense is exercised and the goals aren't bleeding-edge.

The main rule is to arrange that every signal path (ie, address line, decode signal, whatever) has a return path nearby which takes roughly the same route, with no lengthy detours. This implies more or less a grid of ground connections -- and ideally you want the ground pin of every IC to locate at an X-Y intersection of the grid. In practice the grid may be irregular and incomplete, but that's alright -- and, if not, you can always augment the grid later by soldering in some point-to-point ground wires after the fact. It's kinda-sorta like having a 3rd (or even 4th and 5th) layer. That's my $.02 worth, anyway.

BTW, CNC-milling circuit boards is an idea I played with back in the 20th century. I'm tempted to drag out one of the old specimens so I can take some photos to share!

- Jeff

If you look earlier in the thread you can see some of the boards I've already made on my CNC. It's kind of a piece of crap, but it does well for small boards with THT components. As far as going to 4 layer over 2: The problem I ran into was that the return paths were occasionally destroyed, because my ground plane was on the bottom, and if a chip had some signals underneath the ground plane couldn't reach it. The detours were not horribly lengthy, but some of the tracks definitely needed work.

Also, if I end up making a pretty nice board, I can probably sell the extras to people on here looking for a board that does what mine does, I may not be able to get anyone to buy them, but at worst I have spare boards to make more machines. Also, I think having the power and ground planes will definitely help me with signal integrity, since this is sort of my first digital board (at least this complex of one). Ultimately, if I want to hit 16Mhz, I have to have wait states for ROM/NVRAM access, which means adding in a few more chips, that may happen before I'm done here, but honestly, 5-10Mhz is pretty decent as is.

DerTrueForce wrote:

The way this is sounding, you're building something like a PCs motherboard, but 65xx-based. It might be worth designing on similar lines, at least in terms of layout. All the IO ports in one area, and the expansion slots lined up next to one another.

So, I've got all the ports lined up on the "back" of the board, but I may take some of the expansion card slots/headers and line them up too, the issue is, I have 2 VIAs, one controls most of the important stuff, audio, video, text display, the other isn't hooked up to a whole lot (2 expansion headers, and I think possibly the cartridge connector). lining them all up would mix these signals, and probably make it harder to route. I'm messing with the layout right now though, and I think it's going pretty well so far. Although I do have the 816 pressed up against the left side of the board, and all of its busses going to the right and downward. I've done this because I think it will be easier to route this way, but it may bite me.

[backspace119]

So I've got a new layout going, and I think it will work better, although it's a tad bigger than the old one.

here's a picture:

I know it's hard to tell what's going where, but there's a key problem that I need to address here.

VIA1 is up top, oriented horizontally. It connects to the cartridge connector, which is in the bottom area. I'll probably need to switch the cartridge to be connected to VIA2, which is in the bottom right, (U21 if you can see it) surrounded by the SPI stuff.

There aren't any other horrible issues from what I can see, so I think this layout will work better

[Dr Jefyll]

backspace119 wrote:

As far as going to 4 layer over 2: The problem I ran into was that the return paths were occasionally destroyed, because my ground plane was on the bottom, and if a chip had some signals underneath the ground plane couldn't reach it.

Am I missing something? My comments about about two-layer designs are valid for a conventional (ie, etched) two-layer board, and there's no ground plane per se. I assume the comments also apply to your milled CNC boards -- which can do most of the things an etched board can do, isn't that right? (No plate-through vias, I realize, but at the via locations you can solder little stubs in the holes to accomplish the same thing.)

If you can create two independent sets of copper traces, with manually-installed vias, then it seems to me you can make the equivalent of a two-sided etched board.

(However, the milled board gets harder to do as the amount of detail increases -- and even your revised layout contains rather a lot of detail. )

[backspace119]

Dr Jefyll wrote:

backspace119 wrote:

As far as going to 4 layer over 2: The problem I ran into was that the return paths were occasionally destroyed, because my ground plane was on the bottom, and if a chip had some signals underneath the ground plane couldn't reach it.

Am I missing something? My comments about about two-layer designs are valid for a conventional (ie, etched) two-layer board, and there's no ground plane per se. I assume the comments also apply to your milled CNC boards -- which can do most of the things an etched board can do, isn't that right? (No plate-through vias, I realize, but at the via locations you can solder little stubs in the holes to accomplish the same thing.)

If you can create two independent sets of copper traces, with manually-installed vias, then it seems to me you can make the equivalent of a two-sided etched board.

(However, the milled board gets harder to do as the amount of detail increases -- and even your revised layout contains rather a lot of detail. )

Sorry I don't think I described what I meant well. The ground plane (fill area in kicad) wouldn't fill into boxed in areas from signals on the bottom that were running everywhere. I could fix this by using vias to jump into the boxed in area, and then doing another fill, but ultimately it would be a pain and a huge hassle to manage that for all the chips.

My main reasoning for going to 4 layer is simplicity of design on my part. I'm a novice at this at best and I may lack the "common sense" at some points to do things correctly, I may end up going back to two layer, but I'm just exploring the possibility of 4 layer as well.

As for CNCing, there's no way in hell I'd want to fill all the vias for this, if I did CNC something like this, with this many vias, I'd probably try and plate the holes. There's a few resources online for how to do this at home, it involves graphite spraying the board and an electrolysis bath. I've decided that this design is just too detailed and complex for my crappy CNC, if I had a better one, with better etching and milling bits, I could probably do it.