I predict you'll go with 6 layers if you use that FPGA.
Eurocircuits is a great choice for a board manufacturer. I've wanted so badly to try them out for 6 layer boards.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I think should be able to do it with 4 layers. Big advantage of FPGA is that it doesn't matter how you connect most pins, so there won't be much vias needed. The vias cause most of the problems, because they are relatively big (4 trace widths in size) and are present on all layers. And if it gets really crowded I can also make board bigger to give myself a bit more room.

Incrementer stage (bits 4-7) redone properly with good pour flow on all layers. Had to swap bunch of gates so that the output of the incrementer was in proper order for connecting to ADL bus (vertical orange traces on the right)

Finished complete address incrementer (except for bypass caps on bottom)

Upper part of the address bus logic done, plus part of lower part. The remaining lower part are the ICs in the bottom row. I've moved that row up a little bit. It could be moved up a little more, but I want to keep some room for wide ground strips and space for some GND vias. I still need to clean up details, and hook up the control signals.

I've marked a few buses going in/out of this area. The AB/DB buses go out to the FPGA, and the ALU bus goes to output of ALU (to the left). The DB/ALU buses also need to go to lower part of address bus.

Lower part of address bus isn't nearly as crowded, so should go a bit quicker.

Ordered all of the new components so I could fit them on a paper copy to make sure there were no surprises with funny widths or overlapping packages.

Real 65C02 for comparison.

Looks quite nice with all the major IC packages having identical widths.

Address area now completely routed (except for control lines to FPGA and LEDs)

Next up: the register section. About 400 wires left to do in register + ALU section, and then probably another 100 or so that I still need to connect in schematic.

Picture of full board so far. Hooked up register inputs to ALU bus, most of the status flag logic, as well as DB to M register. Down from 400 to 300 wires.

Also added some extra blinkenlights for M register and Data bus.

Added a couple of LEDs for control signals at top of board, plus some text to explain what they are for. Also attached those control signals and address bus to FPGA. Because of the flexible pin allocation of FPGA, it's a fairly painless process (see top screenshot)

Green picture is from the Eurocircuits board viewer.

Great progress! Do you think you're close to ordering a board?

I think at least another week before I can order boards, but two weeks is more likely. I did a bunch of work yesterday, but mostly rerouting old stuff to make room for control bus to FPGA.

I've also worked on the Verilog code. I'm splitting the code up into a separate modules for data path and controls, with proper declaration of all control/status signals. This should make it easier to verify that I have all necessary signals, as well as provide the top level module for the FPGA.

I've already discovered a couple that I forgot, for instance, the control unit needs to look at bit 7 of M register to decide whether a branch crosses a page boundary.

Quick status update. Less than 200 wires left to do on current schematic (mostly in ALU, which is what I'm working on right now). Still need to add control signals, some more LEDs, and stuff like power regulator/oscillator.

ALU fully connected, including input/output buses and flags. Controls not yet connected, but they're all available at the bottom edge. Still need to do some local improvements. There are a couple of design rule violations and some ugly traces.

Wow. Very compact! It’s interesting to see what’s feasible with this package size. Will you also have planes for GND and VCC?

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C74-6502 Website: https://c74project.com

One layer is VCC, the other 3 layers all have GND, but the picture doesn't show the pours. I try to minimize using the inner GND layer for routing, but sometimes it's unavoidable, or it's just better overall. I try to do most of the routing in bottom/VCC layers, and use the top/GND layer for short traces.

Here's a detail of the inner GND layer. I was lazy was some of the traces at the top. I need to take another look and try to put them in bottom layer.