First of all, thank you all for your kind help!
GaBuZoMeu wrote:
but the clock for the 65C02 should not gated by RESET !
Ah! That would have been quite the mistake, making the reset of the 6502 impossible, thank you for spotting it!
GaBuZoMeu wrote:
it should be sufficient to use the 4075 to detect state 7 from the first counter (the one that drives the clock to the 65C02 and drive /PE with that. It takes a few ns to detect state 7 so /PE is not yet valid when bit 7 is shifted out, but when the transition to state 0 happens, the /PE is still low.
I believe I understand your suggestion, I initially considered something similar but I am not very confident about timings and I was afraid I might do something wrong! There is one thing I do not understand: the 4075 is a OR gate, shouldn't I be using a NAND gate to detect state 7 with a low pulse?
BigEd wrote:
If you'd like to look at prior art, I think the Compukit UK101 had this kind of video system - it's almost the same design as the Ohio Superboard's. I think schematics of both can readily be found. But of course, you might well prefer to follow your own path, and that's good too.
cbmeeks wrote:
I don't know if this would help, but if you can find the ULA book from Chris Smith, he does an amazing job of explaining how the ZX Spectrum generated NTSC and PAL video using counters, etc.
Very well written with lots of diagrams.
The ZX Spectrum generated color but you could probably leave some of that out.
Thank you both for your suggestions, I will definitely look into them!
Dr Jefyll wrote:
many of the IC pins with the pin number, rather than the pin name (which of course identifies its function). Although the chips themselves are familiar, most of us don't know the pin numbers by memory.
I am really sorry about that
I drew this scheme initially as a "constructive" diagram before realising I was not sure it would work and deciding to ask for help. Next time I will definitely put pin names!
Dr Jefyll wrote:
In other words, you have a divide-by-eight, with 1 Mhz appearing on the Q2 output. And you can probably use TC to tell your video shift register that it's time to load (rather than shift). If that's not clear I can create a diagram for you (but not this morning).
Thank you very much for your suggestion! So, if I understand correctly, this circuit would provide the same result as GaBuZoMeu's solution?
Dr Jefyll wrote:
Finally, you haven't explained what drives the input of the Character Generator ROM.
I have read Don Lancaster's cheap video solution, and I find it quite fascinating! However, my understanding is that using that approach, a lot of CPU time would be needed to drive the screen, am I correct?
What I was thinking about was to use an other solution mentioned in the forum, i.e. to store the video information (chars in my case) in RAM, and have a counter fetch them while the 6502 is not reading from the data bus (that would be when PHI2 is LOW, am I correct?) using bus transceivers. I am still in the process of understanding all the issues related to this approach, because I started by "the end", i.e. the shift register. I will definitely ask more questions about this in the near future!
I will definitely begin by putting a simple counter to provide the address to the char ROM to test the sistem naturally.
Kind regards,
Davide