Are you using KiCAD? If so, which version?
Who are you choosing to manufacture the boards?

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

No, I'm using Eagle. I'll have the boards made by Eurocircuits.

Experimenting with bus crossings... the problem is that everything is connected to everything else, so no matter how you place the components, it's going to be a mess. And of course, these TSSOP packages are nice and compact, but there's no room to route a trace between the pins, and it starts to get crowded with vias.

When you already a customer to Eurocircuits they surely will give you a quote for a 6 layer board with blind vias. I try to get an estimation online but it won't work. Beta-Layout didn't offer a blind-via option but I'm sure they can produce such boards. But usually asking for a quote is serviced within a few hours.

My assumption for a single board is a price 150..200% of a 4 layer one (without blind vias).


Regards,
Arne

Blind vias are very expensive, because it kicks you out of their pooling service.

But you can stay in the pool with 6 layer and smaller via size, which helps a lot. I'm not at that point yet. Still trying to get everything on 4 layers with standard drill size. There are still plenty of options to explore.

Here's the board so far. I had a lot more traces earlier today, but then I got a better idea for placement. The biggest issue was the placement of the PC/AB LEDs, because there are so many, and they need to be in a row, so it creates a lot of congestion. My first attempt was to give the LED drivers priority placement, but that meant that the high and low parts of the address bus got mixed, creating other problems.

I now have two rows of ICs, top row is MSB address byte, and bottom row is LSB.

Parts list for the complete (hopefully) data path:

• 9 octal D-flipflops (74ALVC574), for: A, X, Y, S, M, PCH, PCL, ABH, ABL. I'm taking out the IR, and moving it into the control unit.
• 8 quad 2-input OR gates for the ALU.
• 12 quad 2-input AND gates, 8 for the ALU and 4 for the address incrementer
• 12 quad 2-input XOR gates, 8 for the ALU and 4 for the address incrementer
• 21 octal tri-state buffers (74ALVC541), used as follows:
  
  • 7 for the AI bus (driving A, X, Y, S, M, PCL, PCH),
  • 5 for the ADH bus (driving ALU, PCH, INC (address incrementer), DB, 00/01/FF)
  • 5 for the ADL bus (driving ALU, PCL, INC, DB, FA/FC/FE),
  • 4 for the data bus (driving ALU, PCH, PCL, P).
• 3 dual D-flipflops with individual CLK inputs (74AUP2G79) for the flags.
• 8 multiplexers 8->1 (74CBT3251) for selecting ALU operation.
• 1 dual 4->1 multiplexer (74CBT3253) for selecting flag input
• 3 quad 2->1 multiplexers (74CBT3257), one used for selecting flag input the other two for selecting BCD adjustment/DB.

A total of 77 ICs. Size varies a bit, but average is something like 6*6 mm, or about 30 cm^2 total area. if you ignore the room needed for routing and LEDs (and the control unit)

This area seemed completely hopeless. These are 4 buffers, from PCL -> AI, PCH -> AI, PCL ->DB and PCH ->DB, plus a set of LEDs. Each of the four 8-bit buses needs to connect to 2 different ICs, and the PCL/PCH buses need to be close to their LEDs, and the AI/DB buses needed to run to other areas of the board as well.

After trying all kinds of via placement, I had an idea to swap to pins on some of the buffers. In the picture, the two buffers in the middle are hooked up straight (e.g. PC0 goes to A0 and AI0 goes to Y0). The buffers on the outside are reversed, so PC0 goes to A7 instead. This is very easy to do in Eagle, by simply defining a 'Straight' and 'Reversed' package option for the same symbol. In the layout, you can then click on an IC, and select the other package. Of course, when you reverse the inputs, you also reverse the outputs, but that worked out great here, because I had the same problem on both sides. Also, very conviently, I can hook up the LEDs for PC[15..12] to PCH->AI buffer, and hook up PC[11:8] to the PCH->DB buffer. The AI bus will connect on the left, and the DB bus connects on the right.

Normally I like to avoid this kind of trickery, because consistency helps to avoid mistakes, but in this case I'm making an exception. Simply changing the package during layout is fool proof, and there's no confusion if I need to debug signals with a scope, because I can just stick the probe on the nearby PC LED pad instead instead of fiddling with the small TSSOP pins.

And I didn't even have to use the GND layer for anything.

For a sense of scale, here's the same set of 4 buffers next to a 65C02 in PLCC socket (with 100 mil grid lines)

Worst (hopefully) is done.

Here's the section around the AB/PC LEDs, including the PCH/PCL->AI/DB drivers at the top, and then below from left to right: PCH register, the PCH->ADH buffer, the ABH register, and the ALU->ADH buffer. Coming from below are two 8-bit buses with the PCL/ABL signals for the LEDs.

Center right is the AB bus leaving, going past the incrementer and out to external memory. Top right is DB leaving, and top left is AI going back to ALU input.

The address incrementer will be placed to the right of this area, and then the INC bus will loop around and come back at the bottom, going into the PCH register.

Had to use all 4 layers for signals, but I think it will be okay.

Beautiful! Loving the compactness of the board design. Not sure if that's a real word...

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

Yeah, and the process of going from "hopeless" to "fits like a glove" is very satisfying.

During all of this, I did neglect to look after the connections for control and supply, and I'm afraid they got buried in the mess, so I'll have to redo part of the design. But, I came up with a different way of doing the long buses under the ICs (the blue/red traces in the bottom row) that will leave a lot more space for intersecting orange traces. Redrawing the actual traces is not a big deal. The most time consuming part is the placement and general flow.

Here's my idea for new bus crossing. Instead of laying out the vias in a diagonal for easy routing on the bus itself, I now have the vias in two vertical lines. This makes the bus (blue/red) a bit less straight, but leaves a lot more space for crossing wires on different layer (shown in yellow here). There's also a smaller gap between the two vertical via columns that could be used for power or additional signals.

Here's the reworked address area with new via placement and straighter lines. This time, all the control signals and GND/VDD are hooked up properly as well as the other signals. Also cleaned up the GND/VDD pours on all the layers, and threw some GND vias near all the ICs (will add some more at the end).

Work in progress. Trying to find good plan for address incrementer. Address bus comes in from the left, LSB in bottom row (yellow/blue), MSB in top row (yellow/red). Because the yellow is the GND plane, I switch those traces back to blue (bottom) as soon as there's room for some vias. Address bus continues to the right for connection to external bus. Output of the incrementer goes down.

First set of AND/XOR gates is connected in rough draft version.

Also picture of current board status (including rat's nest). Address logic in on the right, and the incrementer is in the top right corner.

If I move stuff over a bit, there's just enough room to squeeze the FPGA in the corner.

The bottom row on the right (the ADL bus) can probably move up a bit, but I want to see how much room I need first. That could leave some room for buttons or displays at the bottom.

(that thing looks huge!)