I just updated Verilog code to mimic the block diagram for the ADL/ADH internal address buses. In the block diagram you can see that for instance ADL can be written by:
- ABI, the output of the address incrementer (only bits 7 through 0), for when we want to access same address again, or next one
- output from ALU, for branches, indexed address, or just using the M register as delay.
- DB, for zeropage access. This one is time critical, because it comes from external memory, and we would like to increase access time window.
- PCL (low byte of Program Counter), for when switching back from data processing to instruction fetch
In Verilog, it looks like this. There is a 'sel_adl' select signal that encodes the driver. The 'case' statement looks at that number, and picks the corresponding source signal to drive the internal ADL bus. In case there is no valid select, I write 55 to the bus which should help to catch any mistakes in the simulator.
Code:
always @*
case( sel_adl )
ADL_ABI : ADL = ABI[7:0];
ADL_ALU : ADL = ALU;
ADL_DB : ADL = DB;
ADL_PC : ADL = PCL;
ADL_BRK : ADL = 8'hFE; // fixme, other vectors
default: ADL = 8'h55; // to catch mistakes
endcase
In the schematic, for each possible case, there will be a tri-state bus driver connecting each source to ADL bus. And then the 'sel_adl' will be decoded into individual output enable signals for each of the bus drivers. There are different options for driving the constant signals. I still need to decide on an implementation.
There is similar code for the ADH bus.
Login
Register
FAQ
Search
