6502.org Forum Projects Code Documents Tools Forum
It is currently Fri Nov 22, 2024 11:25 pm

View unanswered posts | View active topics


Board index » 6502.org Users Forum » Programmable Logic

All times are UTC




Post new topic Reply to topic  Page 3 of 3
  [ 34 posts ]  Go to page Previous  1, 2, 3
  Print view Previous topic | Next topic 
Author Message
GaBuZoMeu
 Post subject: Re: CPLD 6502
PostPosted: Wed Jan 02, 2019 7:23 pm 
Offline
User avatar

Joined: Wed Mar 01, 2017 8:54 pm
Posts: 660
Location: North-Germany
Arlet wrote:
Yes. Alternatively, you could instruct the ALU to put a constant on SB, so it will be added to the vector address, maybe to implement a complete interrupt dispatcher.
Thank you.

Arlet wrote:
There's a bug in the code by the way. As you say, 'B' is set in the pushed flags, but it is also set when doing an IRQ. I still need to fix that.
Perhaps you can use IR=00 to set/reset 'B' during push. But I am not familiar with the special situations that (maybe) arise when an IRQ or NMI appears during processing of a BRK instruction. IIRC Drass have had some trouble with spurios interrupts in his TTL approach. Obviously these special situations are not documented - at least as a part of the datasheet.


Regards,
Arne
Top
 Profile  
Reply with quote  
Arlet
 Post subject: Re: CPLD 6502
PostPosted: Wed Jan 02, 2019 7:36 pm 
Offline
User avatar

Joined: Tue Nov 16, 2010 8:00 am
Posts: 2353
Location: Gouda, The Netherlands
Yeah, I need to recheck all the corner cases for IRQ/BRK/NMI happening at the same time. I'm pretty sure there are still some problems.
Top
 Profile  
Reply with quote  
Chromatix
 Post subject: Re: CPLD 6502
PostPosted: Thu Jan 03, 2019 2:10 am 
Offline

Joined: Mon May 21, 2018 8:09 pm
Posts: 1462
On the subject of (zp) addressing mode, it might be worth looking at it as equivalent to (zp,X) or (zp),Y modes with the index replaced by a zero. I don't know whether that helps…
Top
 Profile  
Reply with quote  
Arlet
 Post subject: Re: CPLD 6502
PostPosted: Thu Jan 03, 2019 7:44 am 
Offline
User avatar

Joined: Tue Nov 16, 2010 8:00 am
Posts: 2353
Location: Gouda, The Netherlands
Chromatix wrote:
On the subject of (zp) addressing mode, it might be worth looking at it as equivalent to (zp,X) or (zp),Y modes with the index replaced by a zero.

Yes, that's how it should be done. Right now, the core only has one combined (ZP,X),Y addressing mode with either X or Y replaced by zero, so it would seem to be a simple extension of that idea. The problem is that the extra opcodes don't really fit in the old pattern, so a fairly large amount of extra control logic is needed.

I'll give it a shot later, but I first want to fix the bugs.
Top
 Profile  
Reply with quote  
Display posts from previous:  Sort by  
Post new topic Reply to topic  Page 3 of 3
  [ 34 posts ]  Go to page Previous  1, 2, 3

Board index » 6502.org Users Forum » Programmable Logic

All times are UTC


Who is online

Users browsing this forum: No registered users and 19 guests

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
6502.org is an ongoing project by Mike Naberezny and contributors.