Is PHI-IN normally held high or low in single-step/clock-stopping setups?

Also, which edge starts the cycle: rising or falling? Because the WDC datasheet shows the falling edge first, I assume that's the start. I'm double checking with y'all.

Thanks in advance.

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Thanks for playing.
-- Lord Steve

Falling edge starts a new cycle while concurrently terminating the previous one.

As far as single-stepping is concerned, the WDC 65C02 can have it held in any state indefinitely, since it's a fully static design. Other vendors may have maximum periods though; you'll want to check with their datasheets.

Normally high. WDC's are the only ones that can be stopped indefinitely with phase 0 (and 2) low, and only the high lets you probe the buses and see what you probably want to see. All the CMOS 6502's can be stopped indefinitely with phase 0 high, regardless of brand. NMOS ones cannot be stopped in either one without losing information.


Right. down, then up.