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lordsteve
 Post subject: 65c02 Reset sequence
PostPosted: Fri May 25, 2007 10:50 pm 
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Joined: Wed Jan 22, 2003 6:54 am
Posts: 56
Location: Estados Unidos
I would like to double check that I understand what I have observed empirically. After power-up I assert RESETB low for two cycles. Then I deassert RESETB high and clock 8 cycles. (The datasheet says the reset sequence is 7 cycles, but 1 cycle is the cycle in which RESETB is sampled and detected high.) It seems the the last two cycles are vector pulls (VPB is asserted low).

Does this sound correct?

Thanks.

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GARTHWILSON
 Post subject:
PostPosted: Fri May 25, 2007 11:18 pm 
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Joined: Fri Aug 30, 2002 1:09 am
Posts: 8521
Location: Southern California
Quote:
Does this sound correct?

Yes
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lordsteve
 Post subject: Thank you.
PostPosted: Sat May 26, 2007 2:27 am 
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Thank you.

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