Success!!!
As ttlworks predicted, it wasn’t too hard to get the K24 card going. I had reversed the pins in one of the connectors, and had to make one other patch besides. Then the thing sprung to life!
The C74-SBC has 512K of RAM on-board, and a connector to Garth’s 4MB WM-1 RAM Module. Now that’s a lot of RAM! For now, I just kept to the 8 banks on the SBC, and wrote a little code to exercise the basics (see below). I started by using the C74-6502’s CFG opcode ($42) to enable the 65816 microcode, and to set the K24 AUX bit high. The SBC uses the K24 AUX signal to select the FAST or SLOW clocks, and it was very cool to see the CPU speed up in response. Things were off to a great start!
The test code is very simple. We begin with just writing and reading from high RAM using the “abs lng” addressing mode. It’s very nice to reach into another bank so easily, and I was able to quickly verify that the right things were written to the right banks. I also tried the PLB instruction, and set the Data Bank Register in a quick loop to iterate through the banks. Once again, I was able to confirm that the data was intact, and that absolute addresses correctly followed the DBR in the loop, which was great.
Finally, I got up the nerve for a long jump to another bank — and that went off without a hitch. To celebrate, I wrote a quick little loop to flash some LEDs on A VIA port. It was great to see those LEDs do a little multicolour dance once the whole thing was working. Yay!!! Queue the Mariachi music!
I did discover a problem in the K24 65816 microcode — the PHX and PHY instructions reference the DBR, which is not a good thing when switching banks. Took a little while to figure out what was wrong, but I could clearly see the error in the microcode once I tracked it down. It’s unfortunate, but odds are this is not the only problem. The fact is that, absent a comprehensive test suite, the 65816 microcode is bound to have bugs that will likely remain undetected. Sure makes one appreciate the Dormann 6502 and 65C02 test suites all the more!
Lots more testing to be done, but I think it’s fair to say that ttlworks’ K24 concept is alive and well in the C74-6502! I’m glad we got here Dieter!
I have a couple of demos planned that will make use of the larger address space on the C74-6502, so that will be fun. In the meantime, it’s nice to be chaulking up another milestone — getting closer to the finish line!
Cheers for now,
Drass
Code:
; Check24 -- Run a few checks on the K24 Card
;-----------------------------------------------------------------------------
;
; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/
; command line switches: -l -m -w -h0
; | | | no page headers in listing
; | | wide listing (133 char/col)
; | expand macros in listing
; generate pass2 listing
;-----------------------------------------------------------------------------
org $c000
start lda #$83 ; Select 65816 opcodes + fast clock
db $42, $00 ; C74-6502 CFG opcode, puts A into CFG register
; test lda/sta abs lng
; Store some values in banks 0..7
lda #$00
db $8f, $00, $20, $00 ; sta $002000
lda #$01
db $8f, $00, $20, $01 ; sta $012000 ...
lda #$02
db $8f, $00, $20, $02
lda #$03
db $8f, $00, $20, $03
lda #$04
db $8f, $00, $20, $04
lda #$05
db $8f, $00, $20, $05
lda #$06
db $8f, $00, $20, $06
lda #$07
db $8f, $00, $20, $07
; now check that they are there
db $af, $00, $20, $00 ; lda $002000
cmp #$00
bne error
db $af, $00, $20, $01 ; lda $012000 ...
cmp #$01
bne error
db $af, $00, $20, $02
cmp #$02
bne error
db $af, $00, $20, $03
cmp #$03
bne error
db $af, $00, $20, $04
cmp #$04
bne error
db $af, $00, $20, $05
cmp #$05
bne error
db $af, $00, $20, $06
cmp #$06
bne error
db $af, $00, $20, $07
cmp #$07
bne error
jmp dbr
error jmp error
; Check the values again using DBR
dbr ldx #$07 ; Check the values at $2000
lp1 txa
pha
db $ab ; plb -- points DBR to the bank
cpx $2000
bne error
dex ; ok, next bnk
bpl lp1
; Test running code in bank 4
next lda #$a9 ; put "lda #$aa" at $044000
db $8f, $00, $40, $04
lda #$aa
db $8f, $01, $40, $04
lda #$5c ; put a long jump back
db $8f, $02, $40, $04
lda #lo(back)
db $8f, $03, $40, $04
lda #hi(back)
db $8f, $04, $40, $04
lda #$00
db $8f, $05, $40, $04
db $5c, $00, $40, $04 ; jump to it!
jmp error
back cmp #$aa ; check to see if things went well over there
beq success
jmp error
; Success -- puts on a little light show on the LEDs on the VIA
success lda #00 ; back to bank 0
pha
db $ab
lda #$ff ; Initialize VIA
sta $a000
sta $a001
sta $a002
sta $a003
lda #$41 ; Initialize LEDs to rotate
sta $a000
lda #$5c
db $8f, $00, $40, $04 ; Put a long jump to "loop" in bank 4 at $4000
lda #lo(loop)
db $8f, $01, $40, $04
lda #hi(loop)
db $8f, $02, $40, $04
lda #$00
db $8f, $03, $40, $04
db $5c, $00, $40, $04 ; jump to it!
jmp error
loop inc $1000 ; Freq loop
bne loop
inc $1001
lda $1001
cmp #$40
bne loop
lda #$0
sta $1001
lda $a000 ; bottom row
and #$0f
asl a
cmp #$10
bne skip
lda #$01
skip sta $1002
lda $a000
and #$f0
ora $1002
sta $a000
lda $a000 ;top row
and #$f0
lsr a
cmp #$08
bne skip2
lda #$80
skip2 sta $1002
lda $a000
and #$0f
ora $1002
sta $a000
db $5c, $00, $40, $04 ; jump to it!
nmi_trap
irq_trap jmp irq_trap
org $fffa
dw nmi_trap
dw start
dw irq_trap
end start
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Naturally, any programs that use address $0000 or address $0001 will fail if the 6510 port is enabled on the TTL CPU.[/EDIT]
I have a 1541 Ultimate cartridge on order to be able to run a few of the more demanding demos as a final test, but all indications are that the CPU is indeed cycle-accurate at this point.
