Thanks Garth, yes the datasheet doesn't give any direction on startup so need to make sure I have known values. Even though the early initialisation code will set the ROM and RAM bank selectors in the 6522 port B, I need to know that it will start in the same bank every time during start up or reset.

You could add a ff active on reset to force the ROM/IO selected ignoring the bank output of the VIA, then clear the ff once the first bank setting is done. It’s 1 ff and possibly a gate on the select line. A ‘259 is good for doing this.

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I would have thought that pull-up OR pull-down resistors (say 22k to 47k for pull-ups, May need a lower value for pull-downs) would do the job just fine. Assuming the gates that the 65C22 is feeding are CMOS.

Mark

I think pullups are safer, generally, because they are normal, and you don't end up with a pullup fighting a pulldown.

Yes, I think I will stick the pull ups. The approach of having a flip flop active on reset is nice, but I have no space, so easier to put some weak pull up resistors on the port B output pins, which will feed a 74HC00 NAND gate.

I just need to find some time now to implement this and do some testing. Will report back - thank you for your interest and input.

Hello All

So a quick update. I have spent a few hours on my new decode logic. It seems to work fine at 5.36Mhz, so far it does the following:
- A write to the ROM area always writes to RAM
- Switching out ROM for RAM is good
- RAM banking *almost* works.

So very confused with RAM banking behavior. I basically have pins 4 and 5 of Port B of VIA1 as RAM bank selection 1 of 4 (00 to 11 binary) - diagram on first page of thread shows the logic. I have proven that it all works for 3 banks, but not when both outputs of the NAND gate being fed by port B are high. It seems quite noisy, and therefore what happens is that I get spurious values coming back from RAM.

But more curious is this - it only happens when interrupts are enabled. I have stripped all code from the IRQ handler so it just clears the interrupt and returns, but no difference. Only if I switch off interrups through SEI or disconnect do I get reliable behaviour. But only when the Port B outputs are both 0 (and therefore the NAND output for A16 and A15 are both 0) - every other combination works fine with interrupts running.

I can see noise on the line, but I can't figure this out out at all. I have put lots of 104 (0.1uF) near the decode logic, but no avail. I have also upped the input voltage to the regulator to 12V from 9V but no joy.

The NAND is an LS part driven by WDC6522s - I have pull ups on the outputs which go to A16 and A15 of the SRAM as that is a CMOS part.

Anyone have any theories?

Cheers in advance!

Do you have a full schematic you can post?


I wouldn't expect that to matter. Assuming you are using a 7805-type regulator, stable output can be achieved with as little as 7 volts on the input side.


74LS logic has weak fanout and cannot usually drive its output high enough to constitute a valid logic 1 to CMOS devices. Attempting to overcome this characteristic with a pullup resistor usually produces a slower acting circuit, as the voltage rise beyond the 74LS device's Voh is affect by parasitic capacitance. You need to carefully examine the DC characteristics of your SRAM to see what is specified as the minimum for Vih. As a fairly general rule, this sort of logic mixing should be avoided.

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Thanks for your reply BDD. Yes I tried to account for the LS vs HC situation I have - I am making use of the limited components I have in my possession. The updated schematic is on the first post..

However, I spotted the error after getting my brain properly in to gear. The effect of the memory banking is that when the CPU A15 line goes high accessing RAM, inverse of PB4 and PB5 values are used to map to A15 and A16 of RAM. In short, PB4 and PB5 select which 32K chunk of RAM is enabled. On power up, PB4 and PB5 are high using pull ups and the VIA initialisation code.

So, this is the truth table (A15 is CPU, PBx is port B bits, 16' and 15' are the RAM lines, 32K is the bank number).



What I forgot (or was too stupid to think through) was that PB4 and PB5 being zero forces the use of Bank 3, which is the same bank when A15 is not being selected. Thus I was actually overwriting the same 32K bank that is used for zero page, stack etc.

So slightly embarassed that I didn't figure out the flaw in my programming sooner, but the conclusion is that I now have a fully working memory map with the following features:
- 128K RAM accessed through 4 banks of 32K
- 64K ROM accessed through 4 banks of 16K
- Write to ROM area results in write to shadow RAM (whichever 32K bank is enabled)
- ROM can be disabled for full read and write access to 63K RAM space (continuous from 0x0800-0xffff : 62K)
- Smaller IO area of 1K (previously I had a 4K IO window)

Works stable at 5.36Mhz. I might be able to go higher, but won't be able to try as I am using a 21.4Mhz master clock divided by two to 10.7Mhz for the TMS9918 video chip, and divided by two again for the 5.36Mhz CPU clock.

I now have so much space, especially compared to the 16K ROM, now I will be able to extend the BIOS, Interpreter and File System to be much more sophisticated such as:
- Updating dflat to include floating point, plus extra high resolution drawing commands and ways to use the banked RAM
- Updating the File System to have a proper command line and remove 8.3 and single root folder restriction
- Updating the BIOS, possibly a basic windowing system.

Well, that will keep my project going for many, many more months!

Excellent!

Hi,
Thanks for sharing the info about memory banking. Do you have a link to the complete design of your machine? I'm drawing-up a list for creating my own beast around the WDC '02 and '22 chips. Lots of wishes on the list, now I'm trying to decide which are worthwhile, which are impossible (or just too complicated). Thanks in advance,
Glenn-in-France