jblang wrote:
I assume based on some of stuff I've read though that if I didn't use the PHI2 signal to gate the CS on the LCD, I could get spurious writes to the display.
Certainly the CS signal needs to be gated in
some way, the goal being to prevent writing while the address bus is in transition (ie, is invalid). Otherwise the write may touch an unintended address. If
that happens things won't end well!
IOW, nobody's debating the choice between gating and not gating. The question is between gating with the CPU Phi2 input signal or gating with the CPU Phi2 output signal. For modern WDC parts, the recommendation is to use the CPU Phi2 input signal.
That's not to say that other approaches surely will fail. Heck -- you don't even need to use Phi2 at all, as long as you create or already have available a suitable signal. Mostly that means being true only during the address-valid time and remaining true long enough to satisfy the minimum write time. IOW there's nothing magical about using Phi2 for this purpose -- it simply happens to be convenient.
As for schematics, my preference is the same as Bill's. To each his own, I suppose, but compared with
multiple iterations of "OK, so where the %#^% does this go !?" -- ie, a net list -- I much prefer the so-called rat's nest. (This is general comment -- I'm not addressing jblang in particular.)
No doubt a net list looks tidier, but it only makes sense to the person that already understands. For someone starting from scratch, all the net-list info needs to be traced out and decoded. It's kinda like badly commented source code. The author (who already understands) may fail to realize how helpful the commenting isn't!
A lot depends on the effort and skill of the person who did the drawing. If they were in a hurry and/or didn't care the results will be poor. But a well-drawn schematic is a joy to read.
Sometimes a hybrid solution is best. IOW, draw most or all of the fundamental connections -- the buses, for example. Then a minority of the remaining connections -- the ones that criss-cross all over the place -- can be indicated using signal-names only.
(Maybe I'm stating the obvious, but anyone who hopes to elicit feedback on their project will do well to make the information accessible to readers. That means good commenting in the source code, for example. And -- for Bill and me, at least
-- a schematic that's somewhat drawing-like, not just a list of encoded information.)
-- Jeff
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