PHI2O on WDC 65C02

[jblang]

Looking around the forum and reading the datasheet, I gather that using PHI2O is no longer recommended. Before looking here, I found this out the hard way when my SBC stopped working after I attached a character LCD using these instructions, http://6502.org/mini-projects/optrexlcd/lcd.htm, using PHI2O to feed the NAND gate.

The datasheet doesn't really say why and from the comments here I could only glean that it was because the phase shift of the outputs were not specified so it could lead to timing problems. My problems seemed to go beyond that. When I put anything on PHI2O, or even touch the pin with an unconnected piece of wire, my computer completely stops working. I assume this must have something to do with capacitive loading, but I would like to see if anyone has any further insight. I have switched to using PHI2 input to drive the NAND gate and everything is working now, but I'm still curious if anyone has seen this before or can give a technical explanation about what's going on.

I am using an RC6502 (https://github.com/tebl/RC6502-Apple-1- ... %201%20SBC). Aside from the LCD being connected to the bus as described in the article above, my RC6502 is exactly how the schematic shows it. I am using new WDC versions of both the 65C02 and 65C21.

[cbmeeks]

I have been using PHI2O in my Potpourri6502 SBC. I use it to drive a 65C51 and two 65C22's. Been running smooth at 4MHz for days at a time. I've even cranked it up to 8MHz and it ran fine. Although I didn't do any long-term running at 8MHz.

I've tried two different 65C02's. One from an Apple IIe I have and one from Mouser (couple years old).

[BillO]

A question and a suggestion.

Q: What technique have you used to build this?
S: Try connecting the Phi2 net to Pin 37 of the CPU.


Off topic Comment: I really hate these sorts of schematics. It is so difficult to get a good idea what it going on in the circuit.

Edit: Seems like a bit of over-kill to use two microcontrolers and a 65C21 to implement a console. It would not change the essence of Wozniac's code to just re-write the I/O routines to use a UART.

[jblang]

I'm not sure what you mean by technique. I am using a professionally fabricated PCB made from the KiCad designs in the Github repo, if that's what you mean.

I had already switched to using the clock signal from the PHI2 input on Pin 37, and it solved my problem. My question was just a matter of curiosity. I want to know why connecting anything to PHI2O, even a wire with the other end unconnected, would cause the CPU not to function.

Regarding your critiques, I didn't design this board. Someone sent it to me when we were trading RC2014 PCBs we had manufactured, and I had most of the parts sitting around so I thought I might was well build it. I know it would have been more straightforward to use an ACIA chip, but I think the designer's idea was to keep the circuit as close to the original Apple I as possible. Sorry you don't approve of the schematic but again it wasn't done my me. Personally, though I find this style easier to read than the alternative where there is a rats nest of busses and connections cris-crossing over all over the place.

[BillO]

jblang wrote:

I'm not sure what you mean by technique. I am using a professionally fabricated PCB made from the KiCad designs in the Github repo, if that's what you mean.

Yes, that's what I mean.

Quote:

I had already switched to using the clock signal from the PHI2 input on Pin 37, and it solved my problem. My question was just a matter of curiosity. I want to know why connecting anything to PHI2O, even a wire with the other end unconnected, would cause the CPU not to function.

The WDC65C02 is, regardless of clock speed, much faster at transitioning from one phase to another. Timing has to be kept tighter as this internal speed makes it less tolerant. WDC may have not been too careful about how they internally produced the Phi2O signal making it essentially useless. Given that a system based on any CPU from the original NMOS to the WDC, will run just fine, if not better, by basing the system clock off the signal at pin 37, they may not have seen fit to correct this. I've run in to this more ways than I'd like to admit recently. Needless to say, the WDC65C02 works much better if delay in system clock and it's use (like chip selects, etc.), is kept to an absolute minimum. Maybe others can explain it better.

Quote:

Regarding your critiques, I didn't design this board. Someone sent it to me when we were trading RC2014 PCBs we had manufactured, and I had a spare 6502 and an Arduino sitting around so I thought I might was well build it. I know it would have been more straightforward to use an ACIA chip, but I think the designer's idea was to keep the circuit as close to the original Apple I as possible. Sorry you don't approve of the schematic but again it wasn't done my me. Personally, though I find this style easier to read than the alternative where there is a rats nest of busses and connections cris-crossing over all over the place.

I know it is not your design. Neither was a critique of you, just comments based on my own preferences.

[jblang]

Quote:

The WDC65C02 is, regardless of clock speed, much faster at transitioning from one phase to another. Timing has to be kept tighter as this internal speed makes it less tolerant. WDC may have not been too careful about how they internally produced the Phi2O signal making it essentially useless. Given that a system based on any CPU from the original NMOS to the WDC, will run just fine, if not better, by basing the system clock off the signal at pin 37, they may not have seen fit to correct this. I've run in to this more ways than I'd like to admit recently. Needless to say, the WDC65C02 works much better if delay in system clock and it's use (like chip selects, etc.), is kept to an absolute minimum. Maybe others can explain it better.

I'll keep that in mind. I assume based on some of stuff I've read though that if I didn't use the PHI2 signal to gate the CS on the LCD, I could get spurious writes to the display. As far as what's happening to the chip internally, stray capacitance (or maybe inductance?) on the wire throwing off the CPU's internal clock signal is the only explanation I can see.

Quote:

Neither was a critique of you, just comments based on my own preferences.

No hard feelings. I've seen other 6502 Apple I replica designs I like better, but this is what I have right now. Using an AVR as a glorified UART is definitely overkill. I've seen boards like the L-Star that use the Propeller to provide a keyboard and monitor interface, and eventually I would like to design my own SBC using a 65C816 and a Propeller in which I would probably cut out the PIA entirely. But that project will have to wait until I finish up some other projects. Currently I'm off in Z80-land designing some boards to let me play ColecoVision games on a RC2014.

[Dr Jefyll]

jblang wrote:

I assume based on some of stuff I've read though that if I didn't use the PHI2 signal to gate the CS on the LCD, I could get spurious writes to the display.

Certainly the CS signal needs to be gated in some way, the goal being to prevent writing while the address bus is in transition (ie, is invalid). Otherwise the write may touch an unintended address. If that happens things won't end well!

IOW, nobody's debating the choice between gating and not gating. The question is between gating with the CPU Phi2 input signal or gating with the CPU Phi2 output signal. For modern WDC parts, the recommendation is to use the CPU Phi2 input signal.

That's not to say that other approaches surely will fail. Heck -- you don't even need to use Phi2 at all, as long as you create or already have available a suitable signal. Mostly that means being true only during the address-valid time and remaining true long enough to satisfy the minimum write time. IOW there's nothing magical about using Phi2 for this purpose -- it simply happens to be convenient.


As for schematics, my preference is the same as Bill's. To each his own, I suppose, but compared with multiple iterations of "OK, so where the %#^% does this go !?" -- ie, a net list -- I much prefer the so-called rat's nest. (This is general comment -- I'm not addressing jblang in particular.)

No doubt a net list looks tidier, but it only makes sense to the person that already understands. For someone starting from scratch, all the net-list info needs to be traced out and decoded. It's kinda like badly commented source code. The author (who already understands) may fail to realize how helpful the commenting isn't!

A lot depends on the effort and skill of the person who did the drawing. If they were in a hurry and/or didn't care the results will be poor. But a well-drawn schematic is a joy to read.

Sometimes a hybrid solution is best. IOW, draw most or all of the fundamental connections -- the buses, for example. Then a minority of the remaining connections -- the ones that criss-cross all over the place -- can be indicated using signal-names only.

(Maybe I'm stating the obvious, but anyone who hopes to elicit feedback on their project will do well to make the information accessible to readers. That means good commenting in the source code, for example. And -- for Bill and me, at least -- a schematic that's somewhat drawing-like, not just a list of encoded information.)

-- Jeff

[BigEd]

It does seem odd that even connecting a one-ended wire to the CPU's clock output makes the thing stop working. One possibility is that WDC, in an effort to minimise delay, don't even have an output buffer which serves that pin exclusively: the chip's internal clock signal, well-driven as it must be, just leaves the chip directly. In that case, loading the pin is also loading the internal clock signal. This would surprise me, though.

It's possible that this misbehaviour isn't normal: that the particular CPU you have, jblang, is defective.

Or, maybe, it's possible that something about the design, or your build, has made the CPU extremely susceptible to noise - for example, if you'd installed none of the power decoupling, or if all your capacitors were defective, or something like that. Also seems unlikely!

It certainly surprises me that a one-ended wire can stop the thing working. You're not wrong to wonder about it.

[barrym95838]

BigEd wrote:

It certainly surprises me that a one-ended wire can stop the thing working. You're not wrong to wonder about it.

Back when I was a young'un, we used to call that an "antenna".