Just a quick update! I began having problems with filling layers in order to check the via connections and remembered that I had forgotten that KiCad needs a basic netlist. So rather than wrestle with that fact, I went back and rechecked EPCB Plus today and man am I loving it!

This past week I started the layout with FPGAs and SyncRAMs on EPCB Classic software and laying down the bypass caps in the same manner as I've shown above. When I started the the FPGA interconnections using traces, with the classic software, it locks you in to just a few choices. My choice was .5mm since that's what the FPGA pin spacing is. But I really needed .25mm spacing to get nice and tight, so I decided to give the Plus version a try and it allows you to spec .25mm. It'll even let you spec .225mm! This is freaking awesome, I got the FPGA interconnect done very quickly and it's very tight. I'm stoked. This shouldn't take 4 months like I originally thought. But I will have to just use 4 layers, which I don't think will be a problem.

Cheers!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Update:
1) Finished all the IC footprints on the board.
2) Finished all the connector footprints, except the HDMI.
3) Finished the basic interconnects among the Major IC's, i.e. S6-S6 communication, 2x S6(s) to 4xRAM(s), I2C bus and SPI bus, 16-bit RGB to HDMI IC.
4) Finished the PS routing on the 2nd & 3rd layers for the 1.2V VCCINT and 2.5V VCCAUX. The 2nd layer is mostly 1.8V power plane and the 3rd layer is the GND plane. Top & bottom layers are signal, although the VREGs for 1.2V and 2.5V are mounted there too.

All I have left are the PWR/GND/caps for the HDMI transmitter, some small signals for the CH376 (FAT32 SD Card controller), 256Mb SPI FLASH (extra storage), etc... That's the easy stuff. The most difficult will be digging into the interconnects of JTAG programming the 2 S6's by use of SPI Flash's while using 1 JTAG connector.

Here's a small pic. Sorry had to post it, I know it doesn't mean alot to most.

EDIT: The 2nd plane is 1.8V not 3.3V.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Thanks for the updates.

I'm following along closely as I am planning on making a 65C816 system using a Spartan-6, so it's all really useful information for me, kind of like a tutorial in a way. I'm just trying to lay out my first 4 layer board too and I've picked up a few ideas from this thread that are helpful. It's probably not that it's 4 layer, but with QFP devices and similar dense packages it sure does make the routing a lot harder to figure out. For some reason I forget I put components on both sides of the board and that sure does add to the complexity too.

So even if you don't get many questions or discussion around your updates, I'm sure it's useful to know that we are reading them and learning from them.

That sounds like a potent combo, good luck! 1 thing to remember when interconnecting clock signals from the S6 to an external IC is to make sure it goes to a GCLK pin on the S6, doesn't matter if it's a N_GCLK or P_GLCK. When you start writing the HDL, or doing schematics, ISE will know/recognize what is a clock signal and it will expect it to be constrained to a GCLK pin.

Was in a bit of a rush yesterday, here's the inner layers and how I decided to route VCCAUX and VCCINT. They're not power hungry, so I thought the .025" wide traces from the regulators would suffice. According to this site that should do 1.5A. Really nice calculator that is.

EDIT: Renamed VCCAUX plane.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Been working on the layout just about everyday after work in silence for about 1 hr. I find it very relaxing and sometimes will find glaring mistakes from the previous day. This should decrease over time.
Making only slow progress each day, but it definitely feels like progress is being made, as opposed to '1 step forward, 2 steps backward'. This is a benefit of looking at the design everyday.

Update:
1) Finished most of the power/gnd planes and regulators. The only one left will be a separate 1.8V regulator for the HDMI IC.
2) Finished most of the connectors. I believe the only 1 left is the JTAG. Full size HDMI connector in there for sturdiness as is the USB.
3) Finished the FPGA SPI Flash interconnects.
4) Also, reduced the board size to 2.5" x 4.5"

Things to finish:
1) HDMI IC interconnect to HDMI connector
2) SPI bus to the 256Mb Flash storage IC
3) Bypass caps for secondary IC's, i.e. not SRAM or FPGA (they're done)
4) Add the level shift IC's for the CH376 to communicate with the SD Card
5) Add JTAG connector and figure out dual FPGA interconnect

Here's some pics from the top and bottom (flipped)
You can see that there are indeed 4 SyncRAMs. Tricky stuff

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Here's the schematic from Xilinx UG380 regarding the SPI Flash. I added pin #'s for the 144-pin S6 I'm using and the SPI Flash mentioned in the parts list.
I've chosen not to use resistors in the CCLK path or the DOut from the Flash. But I think it would be wise to make provisions for them in the board layout.
However, the spec'd resistors will be used for both S6's - DONE, PROGRAM and INIT pins. Ignore the JTAG pin assignments for now.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Since this is new to me, I'm not 100% sure this will work (maybe someone can chime in), but this is the way I'll hook up the JTAG pins in order to program each S6 separately. It's going to be abit awkward programming 2 different designs into separate S6's.
I guess I should program the Master S6 first and have it wait for a pattern over the comm bus from the slave. Once the slave is programmed and the slave CPU outputs this pattern, things start running.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Almost done. This will be a power packed 2.5"x4.5" board!
I'm thinking of using a resistive 8"x6" touchscreen instead of a mouse. Also it could double as another very useful input device. I think I was planning for it on an earlier project.

Worked on the layout for quite a few hours yesterday and today. It's becoming an obsession. I will order all parts in the parts list so I can measure them with a micrometer in order to make sure they jive with their datasheets. (The S6's, SyncRam's and CH376T are already in inventory)
Updated parts list.

EDIT: Added the touchscreen connector and IC. It runs off of the I2C bus. (Not shown in these pics)
NOTE: The block diagram needs updating. Just a couple things changed there.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

JTAG wiring Done. Not 100% confident it's going to work but I can cut a trace and solder wire wrap into the vias to make corrections if necessary. Tone of vias for the JTAG, but it's low speed, so that's on the bottom of prioroties.
All bypass cap's done, except for HDMI Transmitter. Will see about a separate isolated 1.8V power section, under the IC, within the 1.8V power plane to isolate noise...
Received all IC's and connectors. Only one incorrect was the 4-pin touchscreen FFC connector. I erroneously ordered the .5mm spacing. 1mm FFC ordered.

I believe the 2 most important things left are the power on reset to the FPGAs and wiring the HDMI Transmitter, power plane, bypass caps and output connector.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Came across a slight challenge doing the layout for the HDMI transmitter IC, the TDA19988. Has an unusual config on the bottom so no exposed vias allowed on the inside area underneath the package, except for the center square which is an exposed connection which must be connected to ground. Luckily not much will have to be redone, in fact I finished all of the rerouting of the vias to the outside perimeter of the IC pins without much problem. There are still plans to make a separate 1.8V dedicated regulator for the VDDanalog, VDDpll and VDDtx pins. Maybe find a real small regulator package just for these 6 pins. The other 1.8V power pins meant for the core and I/O will be connected to the common 1.8V power plane which is on the 2nd layer of the board. Progress! Goal is to be done before New Years.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

90% complete!
HDMI transmitter wired to the HDMI connector. I2C pull-up resistors added. No pull-ups needed for the USB as they're internal to the MCP2200 USB to UART.
There are still 9 pins available on the Slave S6! I must avoid 'mission creep'. Thoughts of I2S, ADC's etc. tempting me, but alas, No!
I think 1 more week where I double check all the pins and I put in the board order to Express PCB. Also, I must double check all the addresses of the I2C devices present on the bus and make sure there's no conflict.
The design currently passes the Design Rule Check.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Added Power on Resets for both S6's /Program lines using the DS1818 3.3V version.
Also I was able to add VIAs for the 9 available/leftover pins on the Slave S6. 3 of them are clock pins, would've been ashame to waste that. So at least they are brought out and I can solder wires into the vias for a future use.
I also labelled all parts on the board. EPCB allows silkscreen on both sides now, with a much wider selection of fonts and sizes. I wasn't going to do this at first but decided it was a good idea. It didn't take much time and it's useful for accounting quantities of certain parts and especially when it comes to soldering. Um, 0402 cap's and res's anyone?
Updated parts list. That's almost complete as well, except the cap's and res's.

I'll post a pic of the board layers soon to the head post.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Don't forget to double-check all the component orientations and pinouts!

The EPCB PLUS software has a feature where one can flip a board, in addition to 'see through' option from the top layer. With a little practice this is a great tool, especially when dealing with 4 layers. But I once caught a mistake where the VReg's on the bottom of the board were mirrored, because I had forgotten I was in see-through mode. Now when working on the bottom layer, I always 'flip' the board.

For the S6's and SyncRams, I'm using proven IC layouts from the PVB project, also the voltage regulators, etc. It does help most of the IC's are on top of the board. 2 of the most critical ones, the SyncRams are on the bottom. I have triple checked those, about to quadruple check...

Also, I was able to get that separate 1.8V power plane for the HDMI transmitter. Not a big deal.

In addition to updating the block diagram, I also intend to post a schematic of the power section. These will be posted in the thread header.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

It sounds as though EPCB "borrowed" that feature from the Copper Connect PCB layout software. Does EPCB Plus output gerbers, or are you still locked into their proprietary format?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!