Interesting, and a thorough ground-up effort by the look of it, decapping chips, photographing, drawing polygons, simulating, and using the original schematics from Donald Hanson. The present state seems to be a (presently oversized) carrier board with an FPGA on it, and a phase accurate model of the 6502.
There is a hope, I think, that once the project is finished, the sources will be made available.
From the nearby thread
MOS 6509 look-alikes?:
mdpenny wrote:
For those who are unsure, the MOS 6509 has a pair of 4-bit memory-mapped registers - at $0000/$0001 - that extend the addressing range of the CPU to 20 bits, or 1MB; one is the "code" register, that is used on most memory accesses, and the other is the "data" register, used on the (the "significant" load/store operation of the) "LDA/STA (zp),Y" instructions (opcodes $B1/$91).
(Where we
see that Jim Brain's 6509 solution is working, is small, and is open-source - hurrah! It won't suit the forum64 purpose precisely, because all the undocumented behaviour of Commodore's various chips are important over there. Also, that's just the 6509 whereas this is capable, or intended to be capable, of being 8 various 6502ish chips.)