Looking carefully at the 4164 datasheet, there are some use-cases described that would be fairly complex to replicate around an SRAM chip. Demultiplexing the address pins would be the easy part; the whole concept of the timing is different, in that the /RAS and /WE lines are edge-triggered with respect to address and data inputs, whereas SRAMS normally expect level-triggered control signals and stable inputs.
It also looks to me as though the output is expected to be held at its original value if a "hidden refresh" (/RAS strobe while /CAS still low) is performed or a "read-modify-write" (/WE strobe while /CAS still low) occurs. So you can't simply assume that latching the high half of the address on every /RAS fall and hard-wiring the SRAM's DQ line(s) to the data I/O pins is appropriate - it might work for some replacements in which those two features go unused, but may result in shorts and malfunctions in other cases.
What's more, the 4164 is a single-bit slice of RAM where most modern SRAMs are 8 bits wide, so the logic would either need to be repeated 8 times, or patch wires extended to the D/Q pins of the other 7 sockets from a master daughterboard fitted to one.
None of this is impossible, of course; it just requires careful implementation. Probably a GAL16V8 and three 8-bit latches could be made to adapt a 64Kx8b SRAM to replace 8x 4164s with some patch wiring.
Other options may include finding directly 4164-compatible chips, not all of which are marked "4164", as this chart illustrates:
http://www.minuszerodegrees.net/memory/4164.htm A newer FPM or EDO DRAM chip could also be used with the caveat that these tend to have shared I/O pins with separate /WE and /OE lines, so the 4164's behaviour of holding the original output valid during a late-write cycle would require latching to emulate.