It's nice to have all the abs addressing modes available for I/O though. BDD even uses the (ZP,X) addressing mode to access I/O.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

However, the Z-80 is slower for any given clock speed and has that horrid assembly language. ☻

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Yep! The (<dp>,X) addressing mode proved to be very useful in accessing the multiple channels of NXP UARTs.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

It really warms the heart knowing that after 40+ years, we're still arguing which is better...the 6502 or Z80. LMAO.


BTW, 6502 is the clear winner.

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Cat; the other white meat.

A common enough misapprehension: for one, the right way to compare the historical MPUs is by comparing systems with equal memory speed. The Z80, historically, took 3 or 4 clock cycles for a machine cycle. The memory cycle was about 3 clock cycles. So, the disparity as seen by MHz comparisons was measuring the wrong thing. But more interesting these days, arguably, is that the modern Z80 has a memory cycle of one clock cycle, which makes it more directly comparable. Over on retrobrewcomputers people are building some rather impressive Z80 and Z280 systems.

It shouldn't be surprising that the Z80 represented some kind of progress, as it was a second generation MPU, designed by an experienced team who worked on the 8080, and it had four times the transistor budget of the 6502.

It is, of course, a bigger machine with a bigger instruction set, which makes it less easy to learn, and is slightly at odds with the minimalist aesthetic of the 6502.

But, de gustibus, and all that.

IOW a Z80 will end up using a higher frequency crystal oscillator, but who cares? It won't affect cost. I'm with Ed on this. The right way to compare the historical MPUs is by comparing systems with equal memory speed. (The misplaced emphasis on clock rate is very prevalent. My remark isn't aimed at BDD in particular.)

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Since we've gotten off on a "which is better" discussion, I too am with Dr Jefyll and BigEd on this subject.

For a long time, the metric that I've used for comparison is memory cycle time. I appreciate that the 6502/65C02 memory cycle period is directly linked to its clock speed, but that is a design choice. Although aesthetically pleasing, a single clock memory cycle is not all that critical. That the memory cycle period of the Zilog/Intel processors is often multiple clock periods in length does allow the designers some flexibility in the timing of the control signals. The single cycle nature of the 6502/65C02 bus almost requires a two phase clock, which brings along its own set of problems.

In fact, the separate read / write strobes of the Zilog/Intel bus is in many ways superior to the ambiguous cycles provided by the single read/write control signal of the 6502/65C02 bus that occur during RMW operations. With separate read / write strobes, the dummy cycles can be just that: no-operation cycles. As Drass has noted elsewhere, some industrious designers have used the R-W-W nature of these dummy cycles to clear interrupt flags. That may appeal to some as a great use of otherwise disruptive, undefined behavior, but I am a bit less enthusiastic on that use of the dummy write cycles.

Note: as pointed out to me by Dr Jefyll, Drass points out in his post here that the RMW cycle is R-W-W for the 6502 and R-R-W for the 65C02. I corrected it above.

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Michael A.