Chromatix wrote:
Actually, it's a pretty important feature for a UART, to be able to indicate when its transmit buffer can accept more data without corrupting previously accepted data. Without it, the only way to transmit successfully is to manually insert a calculated time delay between byte submissions. Even that doesn't account for any flow control imposed by the receiver. Hence I consider the WDC 6551 effectively unusable.
Again— Use a free timer in a VIA, and start it when you store a byte to the transmit data register, either to check for completed time by polling, or use it to generate an interrupt, so the processor can do something else useful while waiting for the byte to go out. No need for a time-wasting delay loop.
You can short CTS\ to DSR\ to check (in the 51's status register) for CTS\ getting negated immediately after storing a byte in the transmit data register to know if it's going to go out or not. If it won't, keep polling periodically until it's no longer negated, then start your VIA timer. Many UARTs don't even have a DSR\ input anymore, so you might not be giving up anything to change its function. If you really do need DSR\ for an actual modem, you can use a spare VIA input bit for CTS\.
None of this is ideal of course; but these are ways to keep the W65C51 usable.
Edit, 2/8/19: I think GaBuZoMeu has the best solution yet: Use the 51's pin 5 (if in DIP), the x16 clock, as an output to drive a VIA's PB6 for its T2 to count pulses and generate an interrupt. The T2 latch value does not need to change with Φ2 rate nor with baud rate. viewtopic.php?f=1&t=5482&p=66433#p66433