I agree.

Either something weird, or else the data lacks sufficient detail to draw conclusions. The way Sergio has overlaid the waveforms on the schematic is helpful but stuff could get lost in the translation. I'm not 100% convinced those tiny images can be blown up and interpreted as literal truth like the readout of a logic analyzer.

On another topic, here's something easy you can check, Sergio. The signal on pin 2 of IC9 should be much the same as the signal on pin 1 -- and likewise for every signal passing through IC9 and IC8. If any signal fails to reproduce then it could indicate IC7/8 defective, or a short in any of the six memory chips or the connections to their address inputs.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

That is why I haven't try to interpret these drawings in depth. It is too easy to get a time shift between different measures.

What puzzles me is the "no activity" of the SY6502 and the R65C02. The SY6502 (I assume it is the original CPU) may be dead. But why should the CMOS one don't work at least a few cycles? The only reason I see is it stays in RESET. (The R65C02 does not provide signals like BE or /ML so it should run.)

A 40/60% clock is simply a violation of the specifications of the datasheets - at least for the SY6502. Further it narrows the address setup window for the VIA to nearly null. I never played with the duty cycle of PHI0. I don't know if there are CPU internals start to behave weird under such circumstances. Using a 50/50% clock simply would cease this possible cause of errors.

Sergio, if you have access to a logic analyzer that would help a lot. Otherwise if you could trace (again) the data and address bus (and R/W, SYNC) by using the rising edge of the /RESet signal as trigger, the traces would be synchron to each other and could then interpreted more reliable. To trigger the reset circuitry it is safe to short the 470nF capacitor.


Regards
Arne

Can you show me? The usual thing is to have no specification for percent duty cycle, only min & max durations for the clock-low period and for the clock-high period. These figures are such that a degree of asymmetry can be tolerated, although there is a limit implied. I talk about this in my Visual Guide to 65xx CPU Timing.

Edit: You're right the clock duty cycle has an effect on the VIA. But my gut feel is that 40/60% is still alright.
Edit: the datasheets you PM'd me confirm a violation at 40/60% at 1 MHz. We agree this might won't necessarily cause trouble, but it might.

I agree the R65C02 should run. Maybe it and the original CPU are both damaged.

Sergio, if I understand properly then you mean there is a pattern of pulses but the pattern never changes, is that right? And, is it true the main pattern is 6 clock cycles long, and that SYNC has a pattern of going high once every three cycles? I would like to double check this, please (as well as the signals on IC9 and IC8 I mentioned in my previous post).

-- Jeff
More photos here.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Yes, there is only a little chance that correcting the duty cycle to 50/50% would be helpful. On the other hand this can be done easily by connecting a can oscillator to p37 - that should not even harm the crystal too much, but removing it would be safer.

And thanks Jeff for the pictures! What a waste of space Today such vast pcb's would cost a fortune.

PCB material looks high quality indeed, IMHO the problem can't be caused by a hairline crack in a PCB trace.

Thanks for the nice schematics and the picture.

Starting to remember, that we had some long term reliability problems at work with that sort of flat cables.
That's when the cable isn't exactly in the correct position when the connector is crimped to the cable,
especially for the bigger connectors.

Could be, that two wires in a flat cable have a connection (short circuit) by accident, or that one wire doesn't have a good connection.
Since the cables are _directly_ connected to the bus, a defective cable could prevent the whole computer from working for good.
Would suggest to check the 40 pin flat cable at connector 'F' first.

Hi to everyone, and sorry for my delay.
I am overcome by such amount of info, so I will try to answer based on my limited knowledge on this topic.

It's important to say the original problem on this machine was a massive battery corrosion which invaded a large part of the CPU board. I understand it was a common trouble which killed several units of this model.
Since that, I had need to clean all the battery leakage, change a lot of component, sockets, and repair several traces. I think I did well that job, because I usually restore that kind of disasters in synthesizers and other analog and hybrid equipment.

The VIA IC (SY6522) was affected by this corrosion, so I replaced it by a R6522.
Also it were affected two RAM chips (HM6116), so I always have tested this unit without the four RAMs, since I though they are not needed, except for to store the patterns. Maybe I was wrong, and they are deeply related in the whole logical function of the entire CPU... I don't know.

However, the funny thing is it "woke up" only once, about 5 years ago, it worked with a certain logic for a few hours, and then it went back into the current state. For that reason, I always understood it had not a massive damage, but something very specific I didn't know how to find.

I've recorded a short video on that occasion, documenting that "resurrection". It can be seen a full logical operation, programming sequence and so. But, when I had tryied to store the pattern, the 2 digits display shown a E1 message. In the owner's manual error list it is described as "E1 = Internal computer stack full".
I've just uploaded that video in my youtube channel if it would be useful for you.
https://www.youtube.com/watch?v=N0FtEaqtmLA

About your suggestions,

- The exact PW ratio of the 1Mhz clock is 63%/37%, so I would need to use a more accurate clock, maybe the can oscilator you suggested me.

- I can't read the EPROM's programs, but I have two pairs of EPROM's: the original ones marked as E51 & F53, and a second pair which I burned in an electronics store with BIN files I've found in a Yahoo Group of Simmons machines owners. I'm attaching those BIN files in this post.

- The F3 input connected to NMI pin has clean +5v on power-up occurs, and after the RESET time it acquires a very high amount of digital noise around those +5v (maybe 0,5 to 0,7v amplitude of noise).

- In the VIA, PA0 to PA7 are in high level with no activity at all. CS1 shows one pulse cycle each 6 clock cycles (similar to A2 address bus waveform) after the RESET time. CS2 shows the same behavior of CPU's NMI pin described above.

- I've tested the continuity of 40pins flat cable ("F" connector) and they are OK. The three 16pins flat cables were tested a lot of times. In fact I've soldered one end of each of them to the smallest related board, to reduce a 50% the contact problems of those unreliable 16pins IC-format connectors.

- About the buffers on the address bus outputs (IC8 & IC9) and the transceivers on the data bus ones (IC7), I did some oscilloscope photos to show you the signal of those busses before and after those stages. The distortion shown in A1 is the same in A0, A2, and the rest of active address busses.
Same happens with data busses. Distortion seen in D0 is the same in rest of data busses. That distortion is entering by the pin 1 (DIR) of IC7, and cames from R/W signal in the segment between the pin 22 of VIA and pin 4 of IC22, but not before that inverter.

- I observed that one cycle in all the busses are equivalent to 6 cycles of 1Mhz clock.

- I don't have a logic analyzer, however, the readouts in all the busses are very statics, like I shown in the schematic.

I'm trying to be as accurate as possible in my observations, I hope it helps to give you some panorama of this dead machine.

Thanks a lot
Sergio

Just to note: it would be a very rare 6502 system which could run with no RAM - almost certainly you will need functioning RAM to get the system running. (But I can't say that's the root cause of the problem.)

Ok, I didn't know that. But the time the machine woke up (years ago), the RAM's were not installed, I'm sure. Although, it shown the E1 error at the end of the pattern programming routine, as shown in the video.

Hmm, not sure how to explain that.

Tomorrow I will go to an electronics store in Barcelona to obtain the 1Mhz can oscillator and, maybe, some nowadays equivalent RAMs of the vintage HM6116 (among other hard-to-find stuff I use to buy there . I will tell you if that produce some changes in the whole behavior of the machine.
Until then...

Yes, this machine will definitely require RAM chips.

Looking at a disassembly of the two ROM images given, the code makes extensive use of zero-page and the stack (lots of JSRs in the startup sequence). I suspect it may have reached the tight loop at $FA00, which is LDX $01 : BNE $FA00, and presumably requires that byte in zero-page to be set by the IRQ handler before it will proceed.

Sergio, modern memory chips have much greater capacity, so if you're unable to find four 6116's, you have the option of using just one larger capacity chip instead. The 6116 stores 2K bytes, so a single 8KB chip (or 32KB or larger) could replace all four 6116's. It's not difficult to modify the original board to accommodate this, so let us know if you're unable to get 6116's.

Good spot! -- that does seems plausible.

( It looks as if it should be possible to read the successive bus values from the drawing by repeatedly drawing a vertical line and assembling those 8 bits into a byte. Do that 6 times and you have the entire 6-cycle sequence. But the bytes spell out a sequence that no 6502 in its right mind would ever perform! Here's why it's nonsense. The waveforms for the individual bits have gotten skewed, timewise -- they don't line up with one another, horizontally. We see they're all shown as beginning with a rising edge, and that seems like a clue. I believe the oscilloscope was set to trigger on the signal that's being observed -- not on an independent, unvarying signal that can serve as a reference. )

Following up on Chromatix's suggestion, here's what I think appears on the address bus and data bus for each cycle of the 6-cycle pattern. Anyone who's curious can print the values in binary then vertically read each column to verify the sequence matches the corresponding waveform (or a skewed version thereof) from the drawing. I haven't checked the actual sequences but the number of 1's in each of the eight columns is as it should be.

• $FA00 - $A6 - opcode of a LDX z-pg instruction
• $FA01 - $01 - operand for the LDX
• $0001 - $01 - here's where the CPU tries to read location $0001, but no device responds
• $FA02 - $D0 - opcode of a BNE
• $FA03 - $FC - operand of the BNE
• $FA04 - $A9 - a "dead cycle" fetch performed as the CPU digests the branch taken

It's doubtful whether this loop at $FA00 is what the CPU ought to be executing. With no RAM, all bets are off! But at least the CPU seems to be behaving rationally, and I find that reassuring with respect to the question about clock duty cycle. (If the behavior were irrational, that could plausibly be the result of seriously bad duty cycle.) But if a 1 MHz oscillator can be obtained then maybe it's a good idea to install it anyway.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Sergio, to me the connections for IC4 (7404) in the schematics look odd.



Starting to wonder, why C10 (4u7) is connected to two output pins of IC4.
Please check if the schematics are correct there.

Would be interesting to know, what the frequency and the duty cycle
of the square wave signal at the /IRQ input of the CPU looks like.

If something goes wrong there, the CPU might go into an "infinite loop".


BTW: PCBs look amazingly clean for a battery leakage, good job on that !

Agreed, it's worth measuring the IRQ input waveform.

If that were a simple RC delay - and it isn't - the time constant is about 0.3mS, which would make for a frequency of about 3kHz. It's going to be very imprecise, but presumably is used for keyboard scanning or display refresh, which is not too timing critical.

Now for that address decoder:



Sorry for the poor quality of the picture: