sburrow wrote:
Isn't there a 'free run' mode for T2 as well?
Interesting question! The datasheet says the shift register can shift in or out
under control of T2 or
free-running at the T2 rate. These modes are selected by ACR bits 4,3,2.
But those are shift-reg modes, not T2 modes. And T2 needs to be able to free-run (ie, self-reload) even when the shift-reg isn't. That's because, even when not free-running, the shift register still has 8 bits that need to be shifted.
So,
clearly T2 is able to reload itself, which implies a latch is present... but the datasheet omits any mention of a T2
high-order latch; it only mentions the T2
low-order latch.
Maybe the T2 high-order latch does exist, and it gets written when the T2 high-order counter (address $9) gets written. Or, (more likely, I suspect) maybe the T2 high-order latch doesn't exist, and when T2 reloads itself the high-order bits get loaded with zero. Can anyone help me shed some light on this?
Back to your RNG, Chad... which is only 8-bit anyway. You also have the option (via ACR bit5) to let T2 count down according to pulses applied on PB6. In this case I expect T2 would, after reaching zero, simply underflow (as you would prefer) rather than self-reloading from the latch... but I haven't tried it, and I haven't pored over the datasheet for clues.
ETA: I overlooked Garth's post until now. But I too suspect the "one-shot" thing only has to do with interrupts. With no solid reason forcing them to stop the timer, the designers would've opted to just let it keep counting. I expect T2 never stops unless it's driven by PB6 and the latter has no activity.
-- Jeff
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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