Because we decided to add that final register downstream you don't need to worry about the '157 result being asynchronous. The XOR and blanking and the whole schmear will get run through the mill and will come out nice & tidy. So, my remark was superfluous -- sorry. In other circumstances it would be relevant, though. If the '157 weren't there you'd need some other way of doing blanking. And a 163 is good for that.
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Nice, I can only find this in HC though is that a problem with a pixel clock of 25MHz?
There used to be such a thing as 'AC163, but I haven't checked lately. 'HC may be marginal, timing-wise. Here's what needs to happen in 40 ns (one pixel-clock period):
- after a rising clock edge there's a propagation delay before the '166 Qh output updates
- the XOR then the '157 process that result, each adding propagation delay
- the output of the 157 must be valid in advance of the subsequent rising clock edge in order to satisfy the input setup time required by the final register.
If the '166, XOR and '157 are AC parts then maybe it's OK if the final register is only HC. If you need certainty then get the relevant figures and see if their sum exceeds 40 ns. Otherwise you can seat-of-the-pants it!
Try whatever's easy (like HC) first -- it'll probably be OK. If not, you'll need AC for the final register.
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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