It appears that my other thread, on designing a debug/bootstrap interface for my project, got derailed somewhat by inaccurate observations about some of the support logic I sketched as part of figuring out the details. So since people seem to be ever so interested in the minutiae of the RDY pin, here's a thread for discussing that specifically.
It turns out that the best support logic is different between three general classes of 6502-family CPU and three levels of functionality - which are not identical sets.
Most people will, at best, use RDY only to indicate to the CPU that they have some slow ROM or other device that needs more than one Phi2 cycle to access. This is easy to support on any of the CPUs by simply ANDing the RDY signals from individual devices (if there's more than one) and driving the RDY pin of the CPU through a current-limiting resistor. If the CPU pulls RDY down to indicate that it's executed a WAI instruction, a few milliwatts will be dissipated in that resistor. If you're definitely using a CPU that doesn't have the WAI instruction (meaning NMOS CPUs and some of the older CMOS devices), you can dispense with the resistor and drive the pin directly.
The first two diagrams in the series below show this in practice; the 65C02 circuit can also be used with the 65816 if required. If you don't even need that level of RDY support, just pull RDY up with that same resistor (or bare wire, if appropriate).
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But if you're concerned about power consumption, say because you intend to run your homebrew machine off solar power and/or small batteries and you expect only intermittent CPU activity, you might want to detect when WAI happens and eliminate all unnecessary power drains henceforth - starting with that resistor attached to the RDY pin. This is the purpose of the latter three diagrams shown below.
The one for the 65C02, subtitled "WAI detection", uses an XOR gate and JK flipflop to detect when the CPU pulls RDY low, assuming that all RDY-producing devices normally drive their lines high. Upon entering the WAI state, therefore, the RDY driver gate will also go low one cycle later, eliminating the power drain through the resistor. The CPU will subsequently be woken up by one of three signals (/IRQ, /NMI, /RST), and these are combined to the opposite input of the JK, restoring the RDY pull-up on the same cycle as the CPU will detect the need to wake up. As a side-effect, a SLEEP signal is produced from the flipflop, which can be used to trigger further power-saving effects elsewhere, such as switching Phi2 to the very efficient 32kHz clock from an RTC chip and powering down the main, power-hungry 8MHz oscillator; this is left as an exercise for the reader.
A simpler version can be implemented for the 65816, making use of the explicit indication of bus inactivity this CPU produces via the VDA and VPA pins, and this is the subject of the fourth diagram. Although not explicitly stated in the datasheet, I expect cycles in WAI will be treated as an indefinitely-long sequence of "internal cycles" keeping VDA and VPA low, so it's not necessary to wait for the CPU to explicitly pull RDY low; we can pull it low ourselves whenever the bus is supposed to be idle, and there will never be sustained static power dissipation through the resistor. But this version doesn't produce that SLEEP signal, so you'd need to perform any additional power-saving steps explicitly in software.
The final circuit is the moral equivalent of the third, but using the '816 bus status instead of the interrupt signals. Note that leaving WAI state may be signalled by either VDA (if fetching an interrupt vector) or VPA (if interrupts were disabled, and execution resumes at the next instruction), so both must be detected to be sure of correctly reasserting RDY in time.
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