BillO wrote:
I'd be willing to bet the price of a shiny new W65C02 that if you loaded one of these GALs with 50K resistor (~20ua) you would see better than 4V at the output. I'd go further to let you test 1000 of them to see if you could find one that did not deliver better than 4V.
Oh, I don't doubt that at all. However, as Garth notes above, the current draw during an output's transition from low to high will be much greater than 20µA, which load will pull down the output voltage until parasitic capacitance has been sufficiently charged. That has the effect of rounding the edges and if sufficiently severe, provoking problems.
Dr Jefyll wrote:
Yes the data sheet cites VDD x 0.8 as the minimum, but it does not say a below-minimum value will fail to be recognized as a logic 1...[WDC is] saying, give us these input voltages or else we have no obligation to meet the speed guarantee (ie, the thing will probably be slower).
The problem, of course, is we don't know just how much those "sub-normal" input voltages affect the MPU's performance. All we know is that despite the "official"
Vih minimum rating of
VDD × 0.8, the MPU seems to function okay with what are TTL outputs from other devices in the system.
BillO wrote:
It is interesting to note too, that you have in your own POC V2.1 several devices including an EPROM and an ATF1504AS CPLD that list that very same 2.4V Voh. The EPROM is actually at a much lower current too.
POC V2.1 is unstable above about 5 MHz. Contrast that with POC V1.1, which is stable at 15 MHz
sans the SCSI host adapter and solid at 12.5 MHz with the host adapter installed. V1.1 uses the same EPROM as V2.x, as well as an SRAM that has
Voh ratings equal to the SRAM in the V2.x units.
So, what is the difference?
POC V1.1 uses 74AC discrete logic, which drives its outputs close to
Vcc and
Gnd, even at the full-load rating of 24mA. Hence the 65C816's control inputs are driven with a very short rise or fall time, since the logic can produce enough current flow to rapidly charge/discharge parasitic capacitance. The ATF1504AS can't do that and while it can produce nearly 4 volts
Voh with the typical CMOS loading (determined by actual measurement), it can't produce that voltage at the beginning of a circuit state change, due to the charging load of the parasitic capacitance.
I should add that both POC V2.0 and V2.1 exhibit essentially identical symptoms when an attempt is made to elevate the Ø2 rate. The principal difference between the two designs is V2.0 has a single QUART and V2.1 has two DUARTs. They both use the same RAM, ROM and CPLD. CPLD code is slightly different between the two, since 2.1 needs an extra chip select for the second DUART. However, the intermediate logic statements in both versions are the same.
I believe the common denominator in this situation may be the
Voh rating of the CPLD when under any significant loading. However, it's not something I've been able to conclusively prove.